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in a terrible botched way, get at I-Cache and set it up
[soc.git]
/
src
/
soc
/
experiment
/
test
/
test_mmu_dcache_pi.py
2021-12-05
Luke Kenneth Casso...
replace yet another duplicate copy of wb_get, possible...
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2021-12-05
Luke Kenneth Casso...
wishbone bus convert on dcache
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2021-12-04
Luke Kenneth Casso...
rename function which needs replacing
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2021-10-08
Tobias Platen
an extra dcbz parameter in all six places
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2021-10-03
Tobias Platen
an extra dcbz parameter in all six places
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2021-05-13
Luke Kenneth Casso...
fix wb_get error where data was being corrupted
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2021-05-12
Luke Kenneth Casso...
add debug info, update comments, disable dcache in...
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2021-05-12
Luke Kenneth Casso...
whoops missing default zero (no idea how)
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2021-05-12
Luke Kenneth Casso...
addcomments for MMU PortInterface test (how it, um...
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2021-05-12
Luke Kenneth Casso...
bit of a hack to get test_mmu_dcache_pi.py operational.
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2021-05-12
Luke Kenneth Casso...
whitespace
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2021-05-11
Luke Kenneth Casso...
pass through MSR.PR through PortInterface, into LoadStore1
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2021-05-09
Luke Kenneth Casso...
add misalign flag to PortInterfaceBase
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2020-10-06
Tobias Platen
test_mmu_dcache_pi.py
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