whoops names changed in MMU FSM
[soc.git] / src / soc / experiment /
2021-05-10 Luke Kenneth Casso... whoops, indentation issue on m.If/m.Else in dcache.py
2021-05-10 Luke Kenneth Casso... add links to set associative image, and bugreport
2021-05-09 Luke Kenneth Casso... update code-comments
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-05-04 Luke Kenneth Casso... wire in exc_o.happened into write-cancellation of LDSTC...
2021-05-04 Luke Kenneth Casso... comments, and change name of LDSTCompUnit exception_o...
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit
2021-05-02 Luke Kenneth Casso... add nc argument to dcache load/store tests
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic...
2021-05-01 Luke Kenneth Casso... dcache store test: data goes in one cycle AFTER valid...
2021-05-01 Cesar StraussAdd GTKWave documents to each DCache unit test
2021-05-01 Luke Kenneth Casso... whitespace
2021-05-01 Luke Kenneth Casso... missing self.
2021-05-01 Luke Kenneth Casso... resolve DriverConflict in TstL0CacheBuffer, really...
2021-04-26 Luke Kenneth Casso... simple regression dcache test was faulty. wishbone...
2021-04-26 Luke Kenneth Casso... incorrect indentation in dcache rams
2021-04-26 Luke Kenneth Casso... simplify dcache test
2021-04-25 Luke Kenneth Casso... spelling mistake
2021-04-25 Luke Kenneth Casso... remove RegStage1.real_adr temporary from dcache
2021-04-25 Luke Kenneth Casso... do not overwrite parameter ra in dcache
2021-04-25 Luke Kenneth Casso... comment out dcache_store from test, not the problem
2021-04-25 Luke Kenneth Casso... remove unneeded code
2021-04-25 Luke Kenneth Casso... read req in wb_in.stall, dcache
2021-04-25 Luke Kenneth Casso... add single regression test for dcache
2021-04-25 Luke Kenneth Casso... add TODO comment in dcache
2021-04-25 Luke Kenneth Casso... move Signals in dcache to relevant context
2021-04-25 Luke Kenneth Casso... dcache Elif used where If should have been
2021-04-25 Luke Kenneth Casso... whoops should be cyc & ~ack
2021-04-25 Luke Kenneth Casso... hard-code dcache stall signal to non-pipelined mode
2021-04-24 Luke Kenneth Casso... increase memory size in dcache test
2021-04-24 Luke Kenneth Casso... increase size of random dcache testing by 10
2021-04-24 Luke Kenneth Casso... fix errors in dcache unit test
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-23 Luke Kenneth Casso... removing more as moved over to openpower-isa
2021-04-22 Luke Kenneth Casso... add debugging and buffering to CacheRam
2021-04-22 Luke Kenneth Casso... whitespace
2021-04-22 Luke Kenneth Casso... r1.end_row_ix off-by-one in dcache
2021-04-22 Luke Kenneth Casso... sync missing in dcache
2021-04-22 Luke Kenneth Casso... dcache.py code-comments
2021-04-22 Luke Kenneth Casso... cleanup dcache
2021-04-22 Luke Kenneth Casso... error using sync, should have been comb
2021-04-21 Luke Kenneth Casso... experimenting with dcache
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2021-04-06 Tobias Platenadd mmu_states.dia
2021-02-24 Tobias Platenwb_get: write outputs to seperate logfile too
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self...
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it...
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore
2021-02-09 colepoirierfix erroneous removal of proof* from experiment/formal...
2021-02-07 colepoirieradd skeleton implementation of experiment/formal/proof_...
2021-02-07 colepoiriericache.py fix formatting
2021-02-07 colepoirierModify experiment/formal/.gitignore because was prevent...
2021-01-10 Tobias Platenadd microwatt mmu config option to compunits.py
2021-01-01 Cesar StraussAdd zero CR test case and fix comments
2021-01-01 Cesar StraussAdd test cases with rc=1
2021-01-01 Cesar StraussMake all ports the same size, on the test ALU
2021-01-01 Cesar StraussAdd CR output port to test cases
2021-01-01 Cesar StraussAdd CR to the output data port
2021-01-01 Cesar StraussMake output write enables independent of valid_o
2021-01-01 Cesar StraussMove NOP test case earlier
2021-01-01 Cesar StraussDisable data value output on NOP
2021-01-01 Cesar StraussAdd condition register (CR) output
2020-12-31 Cesar StraussImplement and test NOP in the test ALU
2020-12-31 Cesar StraussDon't use OP_NOP for zero-delay subtraction
2020-12-31 Cesar StraussTest first input port being masked out
2020-12-31 Cesar StraussSign extend the second input port
2020-12-31 Cesar StraussTest masked-out second input port
2020-12-31 Cesar StraussAdd sign extend to the Test ALU
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave
2020-12-31 Cesar StraussUse the increment operator
2020-12-31 Cesar StraussAdd support for masked write operations
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the...
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit...
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along...
2020-12-30 Cesar StraussTest the rdmaskn control signal
2020-12-29 Cesar StraussRemove left-over comments.
2020-12-13 Cesar StraussAllow more test cases to be run with CXXSim
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-11-24 Cesar StraussFix some typos and whitespace
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow...
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and...
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case
2020-11-19 Cesar StraussSeparate input and output ports by color
2020-11-19 Cesar StraussExplain the test cases
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit...
2020-11-14 Cesar StraussMove the DUT driver to within the test case process
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter
2020-11-01 Cesar StraussAdd a check for liveness.
2020-10-31 Cesar StraussCheck that the read and write counters differ at most...
2020-10-31 Cesar StraussRemove stray comment
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o...
2020-10-24 Cesar StraussCreate a GTKWave document for the test ALU unit tests
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