comment out rlwinm. for now
[soc.git] / src / soc / fu / common_output_stage.py
2020-06-01 Luke Kenneth Casso... minor adjustment, zero test in ALU output stage
2020-05-31 Luke Kenneth Casso... copy in cr0.data into cr0 temp, not whole of cr0 (inclu...
2020-05-31 Luke Kenneth Casso... write cr0 when op.write_cr.ok is set
2020-05-30 Luke Kenneth Casso... set CR0 output when OP_CMP or OP_CMPEQB need it
2020-05-28 Luke Kenneth Casso... update comment
2020-05-24 Luke Kenneth Casso... start using Data in pipelines
2020-05-22 Luke Kenneth Casso... split out Logical Input and Output stages to common...