use copy of FHDLTestCase
[soc.git] / src / soc / fu / cr / test / test_pipe_caller.py
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... use common get_cu_inputs for CR unit tests
2020-06-01 Luke Kenneth Casso... remove reading port 3 for CR pipeline. RS moved to...
2020-06-01 Luke Kenneth Casso... remove unneeded code
2020-05-28 Michael NolanAdd OP_SETB
2020-05-28 Michael NolanFix test_isel to properly examine registers
2020-05-27 Luke Kenneth Casso... rename CROutputData.cr_o to just CROutputData.cr
2020-05-24 Luke Kenneth Casso... add test of reg output, for MFCRF and ISEL
2020-05-23 Luke Kenneth Casso... remove extraneous test_isel
2020-05-23 Luke Kenneth Casso... remove unneeded imports
2020-05-23 Michael NolanAdd test_isel
2020-05-23 Luke Kenneth Casso... add CR_ISEL (and unit test) to CR pipeline
2020-05-21 Luke Kenneth Casso... update CROutputData to use Data()
2020-05-21 Michael NolanAll CR tests now working
2020-05-21 Michael NolanOP_CROP now working
2020-05-21 Michael NolanBegin porting cr pipeline to new interface
2020-05-21 Luke Kenneth Casso... move common functionality between PipeSpecs to soc...
2020-05-21 Luke Kenneth Casso... convert to individual PipeSpecs for each pipeline
2020-05-20 Luke Kenneth Casso... ehn? moo? CR test_pipe_caller locks up 100% CPU on...
2020-05-18 Luke Kenneth Casso... mass-rename of modules to soc.fu.*
2020-05-18 Luke Kenneth Casso... rename pipe to fu