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too much debug info going past, so add the test registers to the
[soc.git]
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src
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soc
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fu
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div
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test
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test_fsm.py
2020-07-22
Jacob Lifshay
fix test_div_state_fsm
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2020-07-19
Luke Kenneth Casso...
if nmigen.sim.pysim import fails use nmigen.back.pysim
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2020-07-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-18
Jacob Lifshay
add div fsm core (`DivState*`) with tests
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