add in privileged instruction decision-making in PowerDecode2
[soc.git] / src / soc / fu / spr /
2020-07-12 Luke Kenneth Casso... rename InternalOp to MicrOp
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Luke Kenneth Casso... add to/from spr test (mtspr, mfspr)
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... adding mtspr tests
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... get/set slow spr in spr test_pipe_caller
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast)
2020-07-04 Luke Kenneth Casso... add spr test, add decode of spr in/out
2020-07-04 Luke Kenneth Casso... add spr main stage
2020-07-04 Luke Kenneth Casso... add spr input record
2020-07-04 Luke Kenneth Casso... add SPR pipeline
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... convenience rename for spr pipe_data.py, consistent...
2020-05-24 Luke Kenneth Casso... add comments for SPR pipe_data
2020-05-24 Luke Kenneth Casso... add SPR pipe_data.py