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[soc.git] / src / soc / litex /
2020-07-23 Luke Kenneth Casso... syntax error tree | commitdiff
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting tree | commitdiff
2020-07-23 Luke Kenneth Casso... try SDRAM SDR tree | commitdiff
2020-07-23 Luke Kenneth Casso... try different MEMTEST_xxx sizes with 64 bit bus width tree | commitdiff
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' tree | commitdiff
2020-07-22 Luke Kenneth Casso... re-add CRG (clock reset generator) tree | commitdiff
2020-07-22 Luke Kenneth Casso... add clock domain using snippet taken from random file tree | commitdiff
2020-07-22 Luke Kenneth Casso... cleanup in litex core.py tree | commitdiff
2020-07-22 Luke Kenneth Casso... update comments tree | commitdiff
2020-07-22 Luke Kenneth Casso... add dummy irq set/get tree | commitdiff
2020-07-22 Luke Kenneth Casso... add boot-helper.S etc from microwatt litex core tree | commitdiff
2020-07-22 Luke Kenneth Casso... missed import of Builder, set cpu_type to "None" tempor... tree | commitdiff
2020-07-22 Luke Kenneth Casso... begin converting litex sim to libre-soc tree | commitdiff
2020-07-22 Luke Kenneth Casso... do not use wildcard import tree | commitdiff
2020-07-22 Luke Kenneth Casso... start from vexriscv sim.py from tree | commitdiff
2020-07-22 Luke Kenneth Casso... correct syntax error tree | commitdiff
2020-07-22 Luke Kenneth Casso... first version of litex core (to be submitted upstream... tree | commitdiff