expand instruction bus width to 64 bit, start on a mini-cache
[soc.git] / src / soc / simple / test / test_issuer.py
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... enable general test cases in test_issuer
2020-06-18 Luke Kenneth Casso... use different way to pass instructions to test_issuer...
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module
2020-06-17 Luke Kenneth Casso... remove unneeded yield
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth Casso... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth Casso... add first version unit test for TestIssuer