src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15
  16
  17 from soc.simple.core import TestIssuer
  18 from soc.experiment.compalu_multi import find_ok # hack
  19
  20 from soc.simple.test.test_core import (setup_regs, check_regs,
  21                                        wait_for_busy_clear)
  22 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  23                                                  check_sim_memory)
  24
  25 # test with ALU data and Logical data
  26 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  27 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  28 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  29 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  30 from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  31 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  32
  33
  34 def setup_i_memory(imem, startaddr, instructions):
  35     mem = imem
  36     print ("insn before, init mem", mem.depth, mem.width, mem)
  37     for i in range(mem.depth):
  38         yield mem._array[i].eq(0)
  39     startaddr //= 4 # assume i-mem is 32-bit wide
  40     for insn, code in instructions:
  41         print ("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  42         yield mem._array[startaddr].eq(insn)
  43         startaddr += 1
  44
  45
  46 class TestRunner(FHDLTestCase):
  47     def __init__(self, tst_data):
  48         super().__init__("run_all")
  49         self.test_data = tst_data
  50
  51     def run_all(self):
  52         m = Module()
  53         comb = m.d.comb
  54         go_insn_i = Signal()
  55
  56         m.submodules.issuer = issuer = TestIssuer()
  57         imem = issuer.imem.mem
  58         core = issuer.core
  59         pdecode2 = core.pdecode2
  60         l0 = core.l0
  61
  62         comb += issuer.go_insn_i.eq(go_insn_i)
  63
  64         # nmigen Simulation
  65         sim = Simulator(m)
  66         sim.add_clock(1e-6)
  67
  68         def process():
  69
  70             for test in self.test_data:
  71                 print(test.name)
  72                 program = test.program
  73                 self.subTest(test.name)
  74                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
  75                           test.msr)
  76                 gen = program.generate_instructions()
  77                 instructions = list(zip(gen, program.assembly.splitlines()))
  78
  79                 pc = 0 # start address
  80
  81                 yield from setup_i_memory(imem, pc, instructions)
  82                 yield from setup_test_memory(l0, sim)
  83                 yield from setup_regs(core, test)
  84
  85                 yield issuer.pc_i.data.eq(pc)
  86                 yield issuer.pc_i.ok.eq(1)
  87
  88                 index = sim.pc.CIA.value//4
  89                 while index < len(instructions):
  90                     ins, code = instructions[index]
  91
  92                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
  93                     print(code)
  94
  95                     # start the instruction
  96                     yield go_insn_i.eq(1)
  97                     yield
  98                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
  99                     yield go_insn_i.eq(0)      # and don't issue a new insn
 100
 101                     # wait until executed
 102                     yield from wait_for_busy_clear(core)
 103
 104                     print ("sim", code)
 105                     # call simulated operation
 106                     opname = code.split(' ')[0]
 107                     yield from sim.call(opname)
 108                     index = sim.pc.CIA.value//4
 109
 110                     # register check
 111                     yield from check_regs(self, sim, core, test, code)
 112
 113                     # Memory check
 114                     yield from check_sim_memory(self, l0, sim, code)
 115
 116         sim.add_sync_process(process)
 117         with sim.write_vcd("issuer_simulator.vcd",
 118                             traces=[]):
 119             sim.run()
 120
 121
 122 if __name__ == "__main__":
 123     unittest.main(exit=False)
 124     suite = unittest.TestSuite()
 125     #suite.addTest(TestRunner(LDSTTestCase.test_data))
 126     #suite.addTest(TestRunner(CRTestCase.test_data))
 127     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 128     #suite.addTest(TestRunner(LogicalTestCase.test_data))
 129     suite.addTest(TestRunner(ALUTestCase.test_data))
 130     #suite.addTest(TestRunner(BranchTestCase.test_data))
 131
 132     runner = unittest.TextTestRunner()
 133     runner.run(suite)
 134