split out front of div into separate stage, still too long combinatorial
[soc.git] / src / soc / simple / test / test_issuer.py
1 """simple core test, runs instructions from a TestMemory
2
3 related bugs:
4
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 """
7
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
10
11 import unittest
12 import sys
13
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc.simple.test.test_runner import TestRunner
20
21 # test with ALU data and Logical data
22 from openpower.test.alu.alu_cases import ALUTestCase
23 from openpower.test.general.overlap_hazards import HazardTestCase
24 from openpower.test.div.div_cases import DivTestCases
25 from openpower.test.mul.mul_cases import MulTestCases2Arg
26 from openpower.test.logical.logical_cases import LogicalTestCase
27 from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase
28 from openpower.test.shift_rot.shift_rot_cases2 import ShiftRotTestCase2
29 from openpower.test.cr.cr_cases import CRTestCase
30 from openpower.test.branch.branch_cases import BranchTestCase
31 from soc.fu.spr.test.test_pipe_caller import SPRTestCase
32 from openpower.test.ldst.ldst_cases import LDSTTestCase
33 from openpower.test.trap.trap_cases import TrapTestCase
34 from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
35 from openpower.simulator.test_helloworld_sim import HelloTestCases
36
37
38 if __name__ == "__main__":
39 svp64 = True
40 if len(sys.argv) > 1 and sys.argv[1] == 'nosvp64':
41 svp64 = False
42 del sys.argv[1]
43
44 # detect overlap case
45 allow_overlap = False
46 if len(sys.argv) >= 2 and sys.argv[1] == '--allow-overlap':
47 allow_overlap = True
48 del sys.argv[1]
49
50 # use in-order issuer, instead of the original FSM based one
51 inorder = False
52 if len(sys.argv) >= 2 and sys.argv[1] == '--inorder':
53 inorder = True
54 del sys.argv[1]
55
56 # allow list of testing to be selected by command-line
57 testing = []
58 for i in reversed(range(1, len(sys.argv))):
59 if not sys.argv[i].startswith('-'):
60 testing.append(sys.argv.pop(i))
61
62 if not testing:
63 testing = ['general', 'ldst', 'cr', 'shiftrot', 'shiftrot2',
64 'logical', 'alu',
65 'branch', 'div', 'mul', 'hazard']
66
67 print("SVP64 test mode enabled", svp64, "overlap",
68 allow_overlap, "in-order", inorder, "testing", testing)
69
70 unittest.main(exit=False)
71 suite = unittest.TestSuite()
72
73 # dictionary of data for tests
74 tests = {'hello': HelloTestCases.test_data,
75 'div': DivTestCases().test_data,
76 'mul': MulTestCases2Arg().test_data,
77 'attn': AttnTestCase.test_data,
78 'general': GeneralTestCases.test_data,
79 'ldst': LDSTTestCase().test_data,
80 'cr': CRTestCase().test_data,
81 'shiftrot': ShiftRotTestCase().test_data,
82 'shiftrot2': ShiftRotTestCase2().test_data,
83 'logical': LogicalTestCase().test_data,
84 'hazard': HazardTestCase().test_data,
85 'alu': ALUTestCase().test_data,
86 'branch': BranchTestCase().test_data,
87 'trap': TrapTestCase().test_data,
88 'spr': SPRTestCase().test_data
89 }
90
91 # walk through all tests, those requested get added
92 for tname, data in tests.items():
93 if tname in testing:
94 suite.addTest(TestRunner(data, svp64=svp64, inorder=inorder,
95 allow_overlap=allow_overlap))
96
97 runner = unittest.TextTestRunner()
98 runner.run(suite)