use get_l0_mem in HDLState to get memory data
[soc.git] / src / soc / simple / test / test_issuer.py
1 """simple core test, runs instructions from a TestMemory
2
3 related bugs:
4
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 """
7
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
10
11 import unittest
12 import sys
13
14 # here is the logic which takes test cases and "executes" them.
15 # in this instance (TestRunner) its job is to instantiate both
16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
17 # simulator. it's also responsible for performing the single
18 # step and comparison.
19 from soc.simple.test.test_runner import TestRunner
20
21 # test with ALU data and Logical data
22 from openpower.test.alu.alu_cases import ALUTestCase
23 from openpower.test.div.div_cases import DivTestCases
24 from openpower.test.logical.logical_cases import LogicalTestCase
25 from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase
26 from openpower.test.cr.cr_cases import CRTestCase
27 from openpower.test.branch.branch_cases import BranchTestCase
28 from soc.fu.spr.test.test_pipe_caller import SPRTestCase
29 from openpower.test.ldst.ldst_cases import LDSTTestCase
30 from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
31 from openpower.simulator.test_helloworld_sim import HelloTestCases
32
33
34 if __name__ == "__main__":
35 svp64 = True
36 if len(sys.argv) == 2:
37 if sys.argv[1] == 'nosvp64':
38 svp64 = False
39 sys.argv.pop()
40
41 # allow list of testing to be selected by command-line
42 testing = sys.argv[1:]
43 sys.argv = sys.argv[:1]
44
45 if not testing:
46 testing = ['general', 'ldst', 'cr', 'shiftrot', 'logical', 'alu',
47 'branch', 'div']
48
49 print ("SVP64 test mode enabled", svp64, testing)
50
51 unittest.main(exit=False)
52 suite = unittest.TestSuite()
53
54 # dictionary of data for tests
55 tests = {'hello': HelloTestCases.test_data,
56 'div': DivTestCases().test_data,
57 'attn': AttnTestCase.test_data,
58 'general': GeneralTestCases.test_data,
59 'ldst': LDSTTestCase().test_data,
60 'cr': CRTestCase().test_data,
61 'shiftrot': ShiftRotTestCase().test_data,
62 'logical': LogicalTestCase().test_data,
63 'alu': ALUTestCase().test_data,
64 'branch': BranchTestCase().test_data,
65 'spr': SPRTestCase().test_data
66 }
67
68 # walk through all tests, those requested get added
69 for tname, data in tests.items():
70 if tname in testing:
71 suite.addTest(TestRunner(data, svp64=svp64))
72
73 runner = unittest.TextTestRunner()
74 runner.run(suite)