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whoops generate core ilang not TestIssuer
[soc.git]
/
src
/
soc
/
simple
/
test
/
2020-06-17
Luke Kenneth Casso...
split out TestIssuer into separate module
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commitdiff
2020-06-17
Luke Kenneth Casso...
remove unneeded yield
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commitdiff
2020-06-17
Luke Kenneth Casso...
enable all tests again in test_core.py and test_issuer.py
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2020-06-17
Luke Kenneth Casso...
got test_issuer FSM operating. bit of a hack
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commitdiff
2020-06-17
Luke Kenneth Casso...
debugging test_issuer, getting FSM working
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2020-06-17
Luke Kenneth Casso...
output to issuer_simulator.vcd
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commitdiff
2020-06-16
Luke Kenneth Casso...
add first version unit test for TestIssuer
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commitdiff
2020-06-16
Luke Kenneth Casso...
reduce instruction depth to 6 bits in TestIssuer
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commitdiff
2020-06-16
Luke Kenneth Casso...
move debug statements to check function
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commitdiff
2020-06-16
Luke Kenneth Casso...
move check regs in simple core to separate function
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commitdiff
2020-06-16
Luke Kenneth Casso...
move test core reg set up into separate function
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commitdiff
2020-06-16
Luke Kenneth Casso...
add beginnings of TestIssuer class, to issue instructio...
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commitdiff
2020-06-16
Luke Kenneth Casso...
refer to signals directly in Test Core
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2020-06-15
Luke Kenneth Casso...
have to set up addr/st rel-go link before setting up...
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2020-06-15
Luke Kenneth Casso...
add in memory setup/check but disable LDST Unit Tests...
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2020-06-08
Luke Kenneth Casso...
re-add unit tests back in
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commitdiff
2020-06-08
Luke Kenneth Casso...
more verbose debug information tracking down SO/OV...
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commitdiff
2020-06-08
Luke Kenneth Casso...
code-morph test_core for XER bit clarity
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commitdiff
2020-06-08
Luke Kenneth Casso...
added check which shows that OV32 in "adde." is not...
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2020-06-07
Luke Kenneth Casso...
assert XER SO/OV/CA registers, check these are ok ...
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2020-06-07
Luke Kenneth Casso...
add debug print statements, re-enable all tests in...
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commitdiff
2020-06-07
Luke Kenneth Casso...
add msr to ISA in test_core.py
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commitdiff
2020-06-06
Luke Kenneth Casso...
missing test.mem arg for ISA in test_core
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commitdiff
2020-06-05
Luke Kenneth Casso...
comment out CR assertion for now
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commitdiff
2020-06-05
Luke Kenneth Casso...
experimenting with CR, not quite right
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commitdiff
2020-06-04
Luke Kenneth Casso...
testing CRs after writing: not in the right bit-order
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commitdiff
2020-06-04
Luke Kenneth Casso...
remove unneeded code
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commitdiff
2020-06-04
Luke Kenneth Casso...
add branch test case to core
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commitdiff
2020-06-04
Luke Kenneth Casso...
no global variables in test suites
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commitdiff
2020-06-04
Luke Kenneth Casso...
sigh. because POWER. CR index inversion
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2020-06-04
Luke Kenneth Casso...
sigh. weirdness involving bit-inversion, inconsistency...
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commitdiff
2020-06-04
Luke Kenneth Casso...
no global variables in test suites
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commitdiff
2020-06-04
Luke Kenneth Casso...
add ShiftRot test case (works only because CRs are...
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commitdiff
2020-06-04
Luke Kenneth Casso...
add both logical and ALU test core
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2020-06-04
Luke Kenneth Casso...
comment clarify on core
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2020-06-04
Luke Kenneth Casso...
initialise XER from simulation
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2020-06-04
Luke Kenneth Casso...
messing with valid/busy signals in core test
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commitdiff
2020-06-04
Luke Kenneth Casso...
test actual reg values being produced in core test
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commitdiff
2020-06-04
Luke Kenneth Casso...
move reg setup to earlier in test
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commitdiff
2020-06-04
Luke Kenneth Casso...
test against Logical (hard-coded change)
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commitdiff
2020-06-04
Luke Kenneth Casso...
add first cut at test core
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commitdiff