assert XER SO/OV/CA registers, check these are ok (fail at the moment)
[soc.git] / src / soc / simple / test /
2020-06-07 Luke Kenneth Casso... assert XER SO/OV/CA registers, check these are ok ...
2020-06-07 Luke Kenneth Casso... add debug print statements, re-enable all tests in...
2020-06-07 Luke Kenneth Casso... add msr to ISA in test_core.py
2020-06-06 Luke Kenneth Casso... missing test.mem arg for ISA in test_core
2020-06-05 Luke Kenneth Casso... comment out CR assertion for now
2020-06-05 Luke Kenneth Casso... experimenting with CR, not quite right
2020-06-04 Luke Kenneth Casso... testing CRs after writing: not in the right bit-order
2020-06-04 Luke Kenneth Casso... remove unneeded code
2020-06-04 Luke Kenneth Casso... add branch test case to core
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth Casso... sigh. weirdness involving bit-inversion, inconsistency...
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... add ShiftRot test case (works only because CRs are...
2020-06-04 Luke Kenneth Casso... add both logical and ALU test core
2020-06-04 Luke Kenneth Casso... comment clarify on core
2020-06-04 Luke Kenneth Casso... initialise XER from simulation
2020-06-04 Luke Kenneth Casso... messing with valid/busy signals in core test
2020-06-04 Luke Kenneth Casso... test actual reg values being produced in core test
2020-06-04 Luke Kenneth Casso... move reg setup to earlier in test
2020-06-04 Luke Kenneth Casso... test against Logical (hard-coded change)
2020-06-04 Luke Kenneth Casso... add first cut at test core