attempt to make carry-in and overflow-enable optional on ALU
[soc.git] / src /
2020-06-03 Luke Kenneth Casso... attempt to make carry-in and overflow-enable optional...
2020-06-03 Luke Kenneth Casso... remove rdflags in pipe_data.py (redundant)
2020-06-03 Luke Kenneth Casso... move over to using power_regspec_map.py from PowerDecod...
2020-06-03 Luke Kenneth Casso... move obtaining simulator data into common function...
2020-06-03 Luke Kenneth Casso... mention TODO on SPR regfile
2020-06-03 Cesar StraussCheck completion of the sub-processes
2020-06-03 colepoirierFixed missing nia.ok.eq(1) in OP_RFID
2020-06-03 colepoirierFixed merge conflict by using remote changes
2020-06-03 Luke Kenneth Casso... tidyup branch. comments
2020-06-03 Luke Kenneth Casso... convenience variables
2020-06-03 Luke Kenneth Casso... FormX not FormXL
2020-06-03 Luke Kenneth Casso... add bit more TODO
2020-06-03 Luke Kenneth Casso... convenience rename for spr pipe_data.py, consistent...
2020-06-03 Cesar StraussSimplify immediate check
2020-06-03 Luke Kenneth Casso... add more TODOs
2020-06-03 Cesar StraussPreliminary check of the alu protocol
2020-06-03 Cesar StraussPass along the operand, in the cycle in which go is...
2020-06-03 colepoirierFixed OP_RFID and OP_SC in fu/trap/main_stage
2020-06-03 Luke Kenneth Casso... add some more constants and ref to POWER9 pdf
2020-06-03 Luke Kenneth Casso... add an if for OP_MTMSR and some comments
2020-06-03 colepoirierAttempted to fix OP_RFID in TRAP pipeline
2020-06-02 colepoirierImplement TRAP instructions OP_RFID and OP_SC
2020-06-02 Luke Kenneth Casso... argh - bad hack, detecting when there are no registers...
2020-06-02 Luke Kenneth Casso... take out unneeded code, add Settle() to see if it helps...
2020-06-02 Luke Kenneth Casso... add lk field to DecodeOut2
2020-06-02 Luke Kenneth Casso... move setting cia input to branch from get_cu_inputs...
2020-06-02 Luke Kenneth Casso... hooray, get_cu_inputs now common to both types of tests
2020-06-02 Luke Kenneth Casso... oooo very annoying. there does not appear to be any...
2020-06-02 Luke Kenneth Casso... add get_inputs function to branch test_pipe_caller
2020-06-02 Luke Kenneth Casso... remove unneeded variable
2020-06-02 Luke Kenneth Casso... Revert "ok ok - for OP_BCREG put CTR in spr2 as well"
2020-06-02 Luke Kenneth Casso... ok ok - for OP_BCREG put CTR in spr2 as well
2020-06-02 Michael NolanSelect spr1 for bcctr - use fast_spr decoding from...
2020-06-02 Luke Kenneth Casso... set up CTR and LR only on BCREG when needed
2020-06-02 Luke Kenneth Casso... decode fast spr for OP_BCREG CTR, TAR and LR
2020-06-02 Luke Kenneth Casso... add TODO comments for read_fast1/2
2020-06-02 Tobias Platenproof_datamerger: proof that output is zero when idle
2020-06-02 Luke Kenneth Casso... debugging branch fast registers
2020-06-02 Michael NolanHandle removal of spr2 field from decoder
2020-06-02 Luke Kenneth Casso... add comment about fast1 and fast2 in branch test_pipe_c...
2020-06-02 Luke Kenneth Casso... add regspecmap function to PowerDecode2
2020-06-02 Michael NolanFix test_bc_reg
2020-06-02 Luke Kenneth Casso... move regspec function to separate module
2020-06-02 Luke Kenneth Casso... add in fast regs support in decoder and into regspec_decode
2020-06-02 Luke Kenneth Casso... add 2nd write-reg for LD/ST Update mode
2020-06-02 Luke Kenneth Casso... add write-regs encoding to regspec decoder
2020-06-02 Luke Kenneth Casso... add read-write register numbering detection
2020-06-02 Luke Kenneth Casso... whoops cut/paste error, creating write_ports not read_ports
2020-06-02 Luke Kenneth Casso... whoops syntax error
2020-06-02 Luke Kenneth Casso... add function expressing the relationship between regspe...
2020-06-02 Luke Kenneth Casso... whitespace
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-02 Luke Kenneth Casso... add MSR constants, TODO translated
2020-06-02 Luke Kenneth Casso... add TODO comments from microwatt source code
2020-06-02 Cesar StraussAllow at least one operand to be fetched
2020-06-02 Cesar StraussHold rdmaskn active during the busy_o cycle
2020-06-01 Luke Kenneth Casso... remove reading port 3 for CR pipeline. RS moved to...
2020-06-01 Luke Kenneth Casso... okaaay add a "rdflags" function which obtains the yes...
2020-06-01 Luke Kenneth Casso... add test_bc_reg (fails)
2020-06-01 Luke Kenneth Casso... remove unneeded fields from Decode2Execute1Type
2020-06-01 Michael NolanAdd proof for RegFile
2020-06-01 Luke Kenneth Casso... more unneeded fields from SR InputRecord
2020-06-01 Luke Kenneth Casso... remove data_len from SR input record
2020-06-01 Luke Kenneth Casso... remove zero/invert from ShiftRot Input Record
2020-06-01 Luke Kenneth Casso... add shift-rot input record and use it
2020-06-01 Luke Kenneth Casso... CompBROpSubset exists
2020-06-01 Luke Kenneth Casso... RS moved to port 1 (from port 3), remove need in ALU...
2020-06-01 Michael NolanAdd proof for RegFileArray
2020-06-01 Luke Kenneth Casso... remove use of reg3 in logical pipeline: CSV files moved...
2020-06-01 Michael NolanHave regfile use AnySeq instead of AnyConst
2020-06-01 Luke Kenneth Casso... rotator carry is set into both XER CA and CA32 fields
2020-06-01 Luke Kenneth Casso... comment out rlwinm. for now
2020-06-01 Luke Kenneth Casso... argh - need to zero the src_i input after "Read" is...
2020-06-01 Michael NolanEnable k-induction for register file proof
2020-06-01 Michael NolanThat was weird. For some reason it wasn't generating...
2020-06-01 Michael NolanFull BMC proof of Register
2020-06-01 Michael NolanBegin rewrite of proof_regfile.py
2020-06-01 Luke Kenneth Casso... put RB in 2nd position (matching immediate) in ShiftRot...
2020-06-01 Luke Kenneth Casso... sigh - another instance where write-mask needed to...
2020-06-01 Luke Kenneth Casso... remove xer so/ov, swap rs/rb to correct(?) order in...
2020-06-01 Tobias Platenproof_datamerger wip
2020-06-01 Luke Kenneth Casso... add rlwinm. test instruction (sets CR0)
2020-06-01 Luke Kenneth Casso... remove duplicate signal
2020-06-01 Luke Kenneth Casso... allow ALU / Logical ops to select RS as 1st operand
2020-06-01 Luke Kenneth Casso... allow M*-Form shiftrot to swap RS/RB back to consistent...
2020-06-01 Luke Kenneth Casso... add first version of ShiftRot CompUnit test
2020-06-01 Luke Kenneth Casso... shiftrot uses LogicalOutputData not ALUOutputData
2020-06-01 Cesar StraussAdd rdmaskn parameter and assert it along issue_i
2020-06-01 Luke Kenneth Casso... add assertions for branch compunit output
2020-06-01 Luke Kenneth Casso... invert SPR1/2 in branch output data
2020-06-01 Luke Kenneth Casso... decode SPRs for branch
2020-06-01 Luke Kenneth Casso... swap over SPR1/2 to fit with microwatt SPR conventions
2020-06-01 Luke Kenneth Casso... add first version compunit branch test
2020-06-01 Luke Kenneth Casso... whoops need to read RS in CR inputs test
2020-06-01 Luke Kenneth Casso... add first version of CR CompUnit test
2020-06-01 Luke Kenneth Casso... minor adjustment, zero test in ALU output stage
2020-06-01 Luke Kenneth Casso... remove unneeded code
2020-05-31 Luke Kenneth Casso... bit-test on the function-unit value being tested
2020-05-31 Luke Kenneth Casso... add logical compunit test
2020-05-31 Luke Kenneth Casso... comment inputs and outputs from ALU unit test
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