2022-09-30 |
Luke Kenneth Casso... | add sv.bc/vs - VLset - test. truncates VL at the vector... |
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2022-09-30 |
Luke Kenneth Casso... | add new sv.bc CTR-loop test, subtracts VL from CTR |
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2022-09-30 |
Luke Kenneth Casso... | whitespace |
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2022-09-30 |
Luke Kenneth Casso... | use regs variables in get_predint |
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2022-09-30 |
Luke Kenneth Casso... | comments |
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2022-09-30 |
Jacob Lifshay | fix pcdec. assembly -- merge into va_form() since it... |
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2022-09-30 |
Jacob Lifshay | rewrite pcdec. pseudocode to work better for JPEG |
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2022-09-30 |
Jacob Lifshay | add lookup table generation for JPEG decode |
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2022-09-30 |
Jacob Lifshay | allow logging function to be overridden for Mem.log_fancy |
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2022-09-29 |
Jacob Lifshay | convert svp64 bigint unittests to use TestAccumulatorBase |
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2022-09-29 |
Jacob Lifshay | finish changing to use adde, not addeo for bigint add |
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2022-09-29 |
Luke Kenneth Casso... | sv.adde not sv.addeo |
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2022-09-29 |
Luke Kenneth Casso... | destination for maddedu and divmod2du for RS defaults... |
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2022-09-29 |
Luke Kenneth Casso... | wowser, complex. implementing maddedu implicit RC/RS... |
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2022-09-29 |
Luke Kenneth Casso... | add carry-roll-over-vector-mul-with-add (!) unit test |
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2022-09-29 |
Luke Kenneth Casso... | comments |
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2022-09-29 |
Luke Kenneth Casso... | add shift-left and shift-right scalar-to-vector tests |
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2022-09-29 |
Luke Kenneth Casso... | update iterators in ISACaller, not used yet |
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2022-09-29 |
Jacob Lifshay | rename madded->maddedu for consistency with PowerISA... |
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2022-09-29 |
Jacob Lifshay | rename divrem2du->divmod2du for consistency with PowerI... |
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2022-09-29 |
Jacob Lifshay | add bigint tests and fix madded pseudocode |
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2022-09-29 |
Jacob Lifshay | add bigint ops |
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2022-09-29 |
Jacob Lifshay | add missing DRAFT comment |
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2022-09-29 |
Jacob Lifshay | fix test_minor_30 |
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2022-09-29 |
Jacob Lifshay | format code |
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2022-09-29 |
Jacob Lifshay | remove unnecesary commented code |
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2022-09-28 |
Luke Kenneth Casso... | srcstep |
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2022-09-28 |
Luke Kenneth Casso... | rename iterators init function |
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2022-09-28 |
Luke Kenneth Casso... | redundant comment |
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2022-09-28 |
Luke Kenneth Casso... | split out svstate update in ISACaller |
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2022-09-28 |
Luke Kenneth Casso... | move failfirst check to separate function in ISACaller |
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2022-09-28 |
Luke Kenneth Casso... | add limit argument to MASK() helper |
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2022-09-28 |
Luke Kenneth Casso... | bugfix reset remaps and get subvl early |
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2022-09-28 |
Luke Kenneth Casso... | comments on horizontal-or |
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2022-09-28 |
Luke Kenneth Casso... | make matrix horizontal-remap example more generic |
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2022-09-28 |
Luke Kenneth Casso... | add horizontal-or-reduction example that thoroughly... |
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2022-09-28 |
Jacob Lifshay | extracting demo JPEG bitstream works |
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2022-09-27 |
Luke Kenneth Casso... | add unpack predicated unit test |
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2022-09-27 |
Luke Kenneth Casso... | hack to check skipping on predicate being all-zero. |
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2022-09-27 |
Luke Kenneth Casso... | sort out predicate loop-skip on pack/unpack |
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2022-09-27 |
Luke Kenneth Casso... | adapt loops to include predicate-mask skipping in ISACaller |
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2022-09-27 |
Jacob Lifshay | add WIP jpeg decoder demo |
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2022-09-26 |
Jacob Lifshay | add more tests and fix missing corner case |
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2022-09-26 |
Jacob Lifshay | pcdec.: change CR0.eq to be early-stop-needed to fit... |
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2022-09-26 |
Jacob Lifshay | add checks for pcdec. once=1 |
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2022-09-26 |
Jacob Lifshay | more cleanup after swapping RA/RB for pcdec. |
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2022-09-26 |
Jacob Lifshay | clean up after lkcl swapped RA/RB for pcdec. |
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2022-09-26 |
Luke Kenneth Casso... | skipping on maskedout elements de-restricted when subst... |
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2022-09-26 |
Luke Kenneth Casso... | add first predicate-mask test of pack/unpack |
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2022-09-26 |
Luke Kenneth Casso... | get pack/unpack tests to use sv.ori to copy sequence... |
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2022-09-26 |
Luke Kenneth Casso... | finally got pack/unpack working |
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2022-09-26 |
Luke Kenneth Casso... | code-morph on loop-end detection in ISACaller |
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2022-09-26 |
Luke Kenneth Casso... | explicit test of src/dststep end-condition in ISACaller... |
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2022-09-26 |
Luke Kenneth Casso... | swap RA/RB so that RA|0 is used not RB|0 |
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2022-09-25 |
Konstantinos Marga... | comment out debug dumps |
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2022-09-25 |
Dmitry Selyutin | test_pysvp64dis: sort ld/st idx stride specs |
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2022-09-25 |
Dmitry Selyutin | power_insn: always provide els for ld/st idx stride |
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2022-09-25 |
Dmitry Selyutin | pysvp64asm: fix VLi attribute access |
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2022-09-25 |
Dmitry Selyutin | power_insn: fix and unify /vli specifier |
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2022-09-25 |
Luke Kenneth Casso... | have to sanity-check dz/zz after full qualifier-process... |
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2022-09-25 |
Luke Kenneth Casso... | add dz/sz assertion in is_bc mode |
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2022-09-25 |
Luke Kenneth Casso... | whitespace |
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2022-09-24 |
Luke Kenneth Casso... | move sea check to after all qualifiers are checked |
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2022-09-24 |
Luke Kenneth Casso... | check variable rather than explicit == LDST_IDX |
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2022-09-24 |
Luke Kenneth Casso... | add elstrided/sea on ldst_idx mode |
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2022-09-24 |
Dmitry Selyutin | test_pysvp64dis: test ld/st idx SEA (simple) |
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2022-09-24 |
Dmitry Selyutin | power_insn: support SEA specifier |
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2022-09-24 |
Dmitry Selyutin | pysvp64asm: support /sea specifier |
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2022-09-24 |
Dmitry Selyutin | consts: introduce SEA field |
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2022-09-24 |
Dmitry Selyutin | pysvp64asm: fix comment layout |
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2022-09-24 |
Luke Kenneth Casso... | set sv_mode to 0b01 in element-strided |
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2022-09-24 |
Luke Kenneth Casso... | frickin frick |
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2022-09-24 |
Luke Kenneth Casso... | add assert to stop failfirst+sea |
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2022-09-24 |
Luke Kenneth Casso... | add extra RC1 test, without VLI. |
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2022-09-24 |
Luke Kenneth Casso... | add RC1 support to ISACaller. |
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2022-09-24 |
Dmitry Selyutin | power_insn: slightly change table checking style |
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2022-09-24 |
Luke Kenneth Casso... | add extra test_pysvp64dis.py test for ff=~RC1/vli mode |
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2022-09-24 |
Luke Kenneth Casso... | whoops got mask/match test wrong in power_insn.py |
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2022-09-24 |
Luke Kenneth Casso... | comment inv,CRbit swap in decode_bo |
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2022-09-24 |
Dmitry Selyutin | sv_binutils: support RS opindex |
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2022-09-24 |
Dmitry Selyutin | power_insn: reorder mode tables to match the spec |
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2022-09-24 |
Dmitry Selyutin | power_insn: rename smr to mr |
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2022-09-24 |
Dmitry Selyutin | sv_binutils: provide Boolean class and Rc field |
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2022-09-24 |
Dmitry Selyutin | power_insn: provide Record.Rc field |
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2022-09-24 |
Dmitry Selyutin | power_insn: simplify rsvd naming; drop unused rsvd |
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2022-09-24 |
Dmitry Selyutin | power_insn: replace Record.function with Record.mode |
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2022-09-24 |
Dmitry Selyutin | pysvp64asm: expand vector register macros |
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2022-09-24 |
Dmitry Selyutin | sv_binutils: support opcodes offset representation |
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2022-09-24 |
Dmitry Selyutin | sv_binutils: fix fields traversal |
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2022-09-24 |
Dmitry Selyutin | power_insn: sort database finally |
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2022-09-24 |
Dmitry Selyutin | power_insn: provide missing cr_in2 properties |
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2022-09-24 |
Dmitry Selyutin | sv_binutils: generate svp64_cr_in2 opindices |
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2022-09-24 |
Dmitry Selyutin | sv_binutils: generate BA opindex |
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2022-09-24 |
Dmitry Selyutin | power_fields: restore class-oriented traversal |
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2022-09-24 |
Jacob Lifshay | pcdec. works! |
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2022-09-23 |
Luke Kenneth Casso... | check svstate (vl) in failfirst test |
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2022-09-23 |
Luke Kenneth Casso... | add data-dependent fail-first mode, Rc=1 variant not... |
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2022-09-23 |
Luke Kenneth Casso... | whoops consistent inversion of inv,CRbit was CRbit,inv |
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2022-09-23 |
Luke Kenneth Casso... | extra failfirst dis tests |
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2022-09-23 |
Luke Kenneth Casso... | remove barse-ackwardsness, use SelectableInt() in decode_bo |
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