run subtest, indentation getting too large, move to function
[soc.git] / src /
2020-07-26 Luke Kenneth Casso... run subtest, indentation getting too large, move to...
2020-07-26 Luke Kenneth Casso... get div compunit test running (use new way to accumulat...
2020-07-26 Luke Kenneth Casso... use new test accumulator class in div tests
2020-07-26 Luke Kenneth Casso... add common test base class for "accumulating" tests...
2020-07-25 Luke Kenneth Casso... remove old div overflow test, keep microwatt version
2020-07-25 Luke Kenneth Casso... hilarious. only just caught a bug where overflow was...
2020-07-25 Luke Kenneth Casso... comb += missing
2020-07-25 Luke Kenneth Casso... add CR0 regression, expected 0b10 actual 0b11
2020-07-25 Luke Kenneth Casso... add regression test 8, DivPipeCore producing spurious...
2020-07-25 Luke Kenneth Casso... add pia back in
2020-07-25 Luke Kenneth Casso... re-add pia_result_to_output function (minus "typing...
2020-07-25 Luke Kenneth Casso... add div compunit test
2020-07-25 Luke Kenneth Casso... wait until pipeline indicates that its output is valid...
2020-07-25 Luke Kenneth Casso... move reset of rdmaskn to after "busy"
2020-07-25 Luke Kenneth Casso... comment LDST FunctionUnit
2020-07-25 Luke Kenneth Casso... going on a bit of a "naming" spree, this for Jean-Paul...
2020-07-25 Luke Kenneth Casso... add spec page numbers to logical ops
2020-07-25 Luke Kenneth Casso... add page-number comments to ALU main_stage
2020-07-25 Luke Kenneth Casso... update comment-headers (TODO include page numbers to...
2020-07-25 Luke Kenneth Casso... make trap proof section more readable
2020-07-24 Samuel A. Falvo IIProperties for MFMSR
2020-07-24 Samuel A. Falvo IIReorganize code layout
2020-07-24 Samuel A. Falvo IIWIP: SC properties more closely match doc'd behavior
2020-07-24 Samuel A. Falvo IIWIP: addressing code review, restoring proofs, etc.
2020-07-24 Luke Kenneth Casso... got fed up with bit-slice ordering crap. cut it out
2020-07-24 Luke Kenneth Casso... add better comments on field_slice
2020-07-24 Luke Kenneth Casso... returned field_slice to original, and added comments
2020-07-24 Luke Kenneth Casso... annoying, yet more typos
2020-07-24 Luke Kenneth Casso... annoying, typo
2020-07-24 Luke Kenneth Casso... better debug assert log message
2020-07-24 Luke Kenneth Casso... too much debug info going past, so add the test registe...
2020-07-24 Luke Kenneth Casso... missed import
2020-07-24 Luke Kenneth Casso... calling the test dictionary from the constructor is...
2020-07-24 Luke Kenneth Casso... whoops spelling
2020-07-24 Luke Kenneth Casso... add the div pipe kind plus prog.assembly to the assert...
2020-07-24 Luke Kenneth Casso... call test_write_ilang only once - ends up being called...
2020-07-24 Luke Kenneth Casso... fix how long div tests run, de-comment FSM and DivPipeCore
2020-07-24 Luke Kenneth Casso... argh! work-in-progress breaking / fixing how to do...
2020-07-24 Luke Kenneth Casso... whoops must add DivTestCasesLong to get it to produce...
2020-07-24 Luke Kenneth Casso... remove bad hack calling trunc_divs/trunc_mods
2020-07-24 Luke Kenneth Casso... re-enable commented-out div unit tests
2020-07-24 Luke Kenneth Casso... split out "all" div into separate unit test (takes...
2020-07-24 Luke Kenneth Casso... reduce variable size, continuation not needed
2020-07-24 Luke Kenneth Casso... comment about timeline does not exist
2020-07-24 Luke Kenneth Casso... ah ha! not using "with" was not calling the "close...
2020-07-24 Luke Kenneth Casso... read into a BytesIO to avoid "too many open files"
2020-07-24 Luke Kenneth Casso... whitespace / comments
2020-07-24 Luke Kenneth Casso... restore modification to caller.py from reversion of...
2020-07-24 Luke Kenneth Casso... Revert "working on div's test_pipe_caller"
2020-07-24 Luke Kenneth Casso... bug found in pseudocode reader when assembly code has...
2020-07-24 Luke Kenneth Casso... code review comments for trap and proof
2020-07-24 Luke Kenneth Casso... made it clear what is meant by the slice numbering...
2020-07-24 Samuel A. Falvo IIRefactorin of common code
2020-07-24 Samuel A. Falvo IIAddress code review comments
2020-07-24 Jacob Lifshayworking on div's test_pipe_caller
2020-07-23 Luke Kenneth Casso... syntax error
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting
2020-07-23 Luke Kenneth Casso... try SDRAM SDR
2020-07-23 Luke Kenneth Casso... allow imem to be 64/32 bit wide
2020-07-23 Luke Kenneth Casso... begin core in running state
2020-07-23 Luke Kenneth Casso... try different MEMTEST_xxx sizes with 64 bit bus width
2020-07-23 Jacob Lifshayadd all div* and mod* instructions to test_pipe_caller
2020-07-22 Jacob Lifshayworking on fsm
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-22 Luke Kenneth Casso... re-add CRG (clock reset generator)
2020-07-22 Luke Kenneth Casso... missing ports from issuer, when doing verilog
2020-07-22 Luke Kenneth Casso... add clock domain using snippet taken from random file
2020-07-22 Luke Kenneth Casso... cleanup in litex core.py
2020-07-22 Luke Kenneth Casso... update comments
2020-07-22 Luke Kenneth Casso... add dummy irq set/get
2020-07-22 Luke Kenneth Casso... add boot-helper.S etc from microwatt litex core
2020-07-22 Luke Kenneth Casso... set additional MSR bits according to v3.0B spec when...
2020-07-22 Luke Kenneth Casso... use (new) MSRb and PIb which has auto-bigendian numbers
2020-07-22 Luke Kenneth Casso... sigh, auto-create some little/big-endian classes for...
2020-07-22 Luke Kenneth Casso... missed import of Builder, set cpu_type to "None" tempor...
2020-07-22 Luke Kenneth Casso... begin converting litex sim to libre-soc
2020-07-22 Luke Kenneth Casso... whoops forgot field accessor
2020-07-22 Luke Kenneth Casso... do not use wildcard import
2020-07-22 Luke Kenneth Casso... start from vexriscv sim.py from
2020-07-22 Luke Kenneth Casso... correct syntax error
2020-07-22 Luke Kenneth Casso... first version of litex core (to be submitted upstream...
2020-07-22 Luke Kenneth Casso... whoops typo, 63-start not 3-start (doh)
2020-07-22 Luke Kenneth Casso... field number ordering wrong way round?
2020-07-22 Luke Kenneth Casso... syntax error
2020-07-22 Luke Kenneth Casso... review trap main_stage.py modifications: we are not...
2020-07-22 Luke Kenneth Casso... comments, add page spec numbers for branch ops into...
2020-07-22 Luke Kenneth Casso... add comment headings with spec page numbers
2020-07-22 Luke Kenneth Casso... comment on op.insn ordering
2020-07-22 Luke Kenneth Casso... code-shuffle, add comments
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input...
2020-07-22 Luke Kenneth Casso... inline comments in trap proof
2020-07-22 Luke Kenneth Casso... note that traptype MUST increase in bitwidth correspond...
2020-07-22 Luke Kenneth Casso... fix branch main_stage proof, add ctr 32-bit, fix BCREG
2020-07-22 Luke Kenneth Casso... rework branch proof to use br_input_record
2020-07-22 Luke Kenneth Casso... update README for pipe_data.py
2020-07-22 Luke Kenneth Casso... reduce number of FastRegs read ports
2020-07-22 Luke Kenneth Casso... comments on what goes into CommonPipeSpec
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions.
2020-07-22 Samuel A. Falvo IIPEP8 compliance
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