soc.git
4 years agoconvert microwatt rotator to nmigen (first draft)
Luke Kenneth Casson Leighton [Mon, 11 May 2020 10:29:49 +0000 (11:29 +0100)]
convert microwatt rotator to nmigen (first draft)

4 years agoAdd test for rlwnm
Michael Nolan [Sun, 10 May 2020 22:55:16 +0000 (18:55 -0400)]
Add test for rlwnm

4 years agoImplement rlwimi as well
Michael Nolan [Sun, 10 May 2020 22:52:45 +0000 (18:52 -0400)]
Implement rlwimi as well

4 years agoImplement rlwinm in alu
Michael Nolan [Sun, 10 May 2020 20:05:23 +0000 (16:05 -0400)]
Implement rlwinm in alu

4 years agoAdd test for rlwinm
Michael Nolan [Sun, 10 May 2020 20:03:35 +0000 (16:03 -0400)]
Add test for rlwinm

4 years agoReduce BMC depth on proof_main_stage.py
Michael Nolan [Sun, 10 May 2020 16:26:27 +0000 (12:26 -0400)]
Reduce BMC depth on proof_main_stage.py

4 years agouse temporary python vars rather than copy signals (shorter code)
Luke Kenneth Casson Leighton [Sun, 10 May 2020 05:42:43 +0000 (06:42 +0100)]
use temporary python vars rather than copy signals (shorter code)

4 years agoAdd shift left and shift right to main stage proof
Michael Nolan [Sat, 9 May 2020 23:22:28 +0000 (19:22 -0400)]
Add shift left and shift right to main stage proof

4 years agosigh ton of syntax errors
Luke Kenneth Casson Leighton [Sat, 9 May 2020 18:25:55 +0000 (19:25 +0100)]
sigh ton of syntax errors

4 years agobit of reorg, trick on add - put carry in into the LSB
Luke Kenneth Casson Leighton [Sat, 9 May 2020 18:19:20 +0000 (19:19 +0100)]
bit of reorg, trick on add - put carry in into the LSB

4 years agocomment output stage
Luke Kenneth Casson Leighton [Sat, 9 May 2020 17:48:27 +0000 (18:48 +0100)]
comment output stage

4 years agocomment maskgen
Luke Kenneth Casson Leighton [Sat, 9 May 2020 17:33:20 +0000 (18:33 +0100)]
comment maskgen

4 years agoHandle algebraic shifts too
Michael Nolan [Sat, 9 May 2020 17:21:07 +0000 (13:21 -0400)]
Handle algebraic shifts too

4 years agoImplement logical shift right
Michael Nolan [Sat, 9 May 2020 17:06:48 +0000 (13:06 -0400)]
Implement logical shift right

4 years agoAdd support for sld
Michael Nolan [Sat, 9 May 2020 17:03:52 +0000 (13:03 -0400)]
Add support for sld

4 years agoChange shift left to be implemented with rotate and mask
Michael Nolan [Sat, 9 May 2020 17:00:14 +0000 (13:00 -0400)]
Change shift left to be implemented with rotate and mask

4 years agoAdd mask generator for shift class instructions
Michael Nolan [Sat, 9 May 2020 15:58:19 +0000 (11:58 -0400)]
Add mask generator for shift class instructions

4 years agoAdd shift left opcode to main_stage
Michael Nolan [Sat, 9 May 2020 15:18:53 +0000 (11:18 -0400)]
Add shift left opcode to main_stage

4 years agoFix broken mask when x == y
Michael Nolan [Sat, 9 May 2020 15:15:34 +0000 (11:15 -0400)]
Fix broken mask when x == y

4 years agoAdd right shift test to test_caller.py
Michael Nolan [Sat, 9 May 2020 14:57:31 +0000 (10:57 -0400)]
Add right shift test to test_caller.py

4 years agoAdd shift test to test_caller, fix fixedshift being weird on 32 bit shifts
Michael Nolan [Sat, 9 May 2020 14:51:44 +0000 (10:51 -0400)]
Add shift test to test_caller, fix fixedshift being weird on 32 bit shifts

4 years agoFix helpers.py not playing nicely with selectableInts
Michael Nolan [Sat, 9 May 2020 14:47:00 +0000 (10:47 -0400)]
Fix helpers.py not playing nicely with selectableInts

4 years agoAdd reversed add and subtract, as well as lshift and rshift
Michael Nolan [Sat, 9 May 2020 14:41:29 +0000 (10:41 -0400)]
Add reversed add and subtract, as well as lshift and rshift

4 years agocomment where ALUIntermediateData to go
Luke Kenneth Casson Leighton [Sat, 9 May 2020 14:06:02 +0000 (15:06 +0100)]
comment where ALUIntermediateData to go

4 years agoTODO on AluIntermediateData
Luke Kenneth Casson Leighton [Sat, 9 May 2020 14:04:55 +0000 (15:04 +0100)]
TODO on AluIntermediateData

4 years agomissing sticky-overflow pass-through from middle stage
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:59:30 +0000 (14:59 +0100)]
missing sticky-overflow pass-through from middle stage

4 years agopass through sticky-overflow
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:56:16 +0000 (14:56 +0100)]
pass through sticky-overflow

4 years agoremove unneeded class
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:56:02 +0000 (14:56 +0100)]
remove unneeded class

4 years agoclarifying comments
Luke Kenneth Casson Leighton [Sat, 9 May 2020 13:54:34 +0000 (14:54 +0100)]
clarifying comments

4 years agoMinor cleanup
Michael Nolan [Sat, 9 May 2020 13:19:26 +0000 (09:19 -0400)]
Minor cleanup

4 years agopreliminary test for LD/ST "update" mode working
Luke Kenneth Casson Leighton [Sat, 9 May 2020 11:18:11 +0000 (12:18 +0100)]
preliminary test for LD/ST "update" mode working

4 years agodocument PowerOp
Luke Kenneth Casson Leighton [Sat, 9 May 2020 10:58:54 +0000 (11:58 +0100)]
document PowerOp

4 years agoadd comments
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:01:22 +0000 (00:01 +0100)]
add comments

4 years agoadd ALUFirstInputData
Luke Kenneth Casson Leighton [Fri, 8 May 2020 23:01:12 +0000 (00:01 +0100)]
add  ALUFirstInputData

4 years agosend address to memory only for one cycle and acknowledge LD immediately
Luke Kenneth Casson Leighton [Fri, 8 May 2020 21:29:55 +0000 (22:29 +0100)]
send address to memory only for one cycle and acknowledge LD immediately
in test-L0CacheBuffer

4 years agoexperimenting
Luke Kenneth Casson Leighton [Fri, 8 May 2020 21:13:51 +0000 (22:13 +0100)]
experimenting

4 years agoworking indexed version of LD/ST CompUnit
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:54:19 +0000 (21:54 +0100)]
working indexed version of LD/ST CompUnit

4 years agohmmm i think LD/ST Comp Unit might actually be working...
Luke Kenneth Casson Leighton [Fri, 8 May 2020 20:45:42 +0000 (21:45 +0100)]
hmmm i think LD/ST Comp Unit might actually be working...

4 years agoOops, forgot pipeline.py
Michael Nolan [Fri, 8 May 2020 20:35:40 +0000 (16:35 -0400)]
Oops, forgot pipeline.py

4 years agoAdd tests for immediates, add subf to tests
Michael Nolan [Fri, 8 May 2020 20:34:57 +0000 (16:34 -0400)]
Add tests for immediates, add subf to tests

4 years agoAdd comments about the purpose of each alu stage
Michael Nolan [Fri, 8 May 2020 20:11:41 +0000 (16:11 -0400)]
Add comments about the purpose of each alu stage

4 years agoAdd test for alu against simulator
Michael Nolan [Fri, 8 May 2020 19:55:26 +0000 (15:55 -0400)]
Add test for alu against simulator

4 years agoAdd assertions for output stage cr0
Michael Nolan [Fri, 8 May 2020 18:59:45 +0000 (14:59 -0400)]
Add assertions for output stage cr0

4 years agoAdd output stage
Michael Nolan [Fri, 8 May 2020 18:51:58 +0000 (14:51 -0400)]
Add output stage

4 years agoAdd and or and xor to main_stage
Michael Nolan [Fri, 8 May 2020 17:56:37 +0000 (13:56 -0400)]
Add and or and xor to main_stage

4 years agoAdd carry in and out
Michael Nolan [Fri, 8 May 2020 17:52:30 +0000 (13:52 -0400)]
Add carry in and out

4 years agoHave input_stage set the b operand to imm_data if it is valid
Michael Nolan [Fri, 8 May 2020 17:49:27 +0000 (13:49 -0400)]
Have input_stage set the b operand to imm_data if it is valid

4 years agoAdd extra bits (carry, overflow, etc) to input and output structs
Michael Nolan [Fri, 8 May 2020 17:32:35 +0000 (13:32 -0400)]
Add extra bits (carry, overflow, etc) to input and output structs

4 years agoBegin adding main ALU stage
Michael Nolan [Fri, 8 May 2020 17:23:09 +0000 (13:23 -0400)]
Begin adding main ALU stage

4 years agoConvert alu to use the op in ctx
Michael Nolan [Fri, 8 May 2020 16:35:51 +0000 (12:35 -0400)]
Convert alu to use the op in ctx

4 years agoAdd FPPipeContext to alu pipe_data
Michael Nolan [Fri, 8 May 2020 15:56:09 +0000 (11:56 -0400)]
Add FPPipeContext to alu pipe_data

4 years agoalmost got LD/ST CompUnit working
Luke Kenneth Casson Leighton [Fri, 8 May 2020 15:31:10 +0000 (16:31 +0100)]
almost got LD/ST CompUnit working

4 years agoprototype LD/ST L0 cache/buffer was bouncing address-acknowledgement up
Luke Kenneth Casson Leighton [Fri, 8 May 2020 12:16:07 +0000 (13:16 +0100)]
prototype LD/ST L0 cache/buffer was bouncing address-acknowledgement up
and down.  clear the latch during the "reset" phase and it works now

4 years agoAdd handling of A inversion and B input
Michael Nolan [Fri, 8 May 2020 15:09:40 +0000 (11:09 -0400)]
Add handling of A inversion and B input

4 years agoBegin adding input stage of alu
Michael Nolan [Fri, 8 May 2020 15:03:34 +0000 (11:03 -0400)]
Begin adding input stage of alu

4 years agoAdd pipe data for ALU pipeline
Michael Nolan [Fri, 8 May 2020 14:43:32 +0000 (10:43 -0400)]
Add pipe data for ALU pipeline

4 years agoUpdate gitignore in isa dir
Michael Nolan [Fri, 8 May 2020 14:41:23 +0000 (10:41 -0400)]
Update gitignore in isa dir

4 years agoSeparate out ALU Input record from alu_hier.py
Michael Nolan [Fri, 8 May 2020 14:40:06 +0000 (10:40 -0400)]
Separate out ALU Input record from alu_hier.py

4 years agoAdd test_branch_loop_ctr
Michael Nolan [Thu, 7 May 2020 19:54:32 +0000 (15:54 -0400)]
Add test_branch_loop_ctr

4 years agoAdd tests for conditional branches
Michael Nolan [Thu, 7 May 2020 19:41:06 +0000 (15:41 -0400)]
Add tests for conditional branches

4 years agomove unused simulator code out the way
Luke Kenneth Casson Leighton [Thu, 7 May 2020 18:35:32 +0000 (19:35 +0100)]
move unused simulator code out the way

4 years agotesting LD without ST
Luke Kenneth Casson Leighton [Thu, 7 May 2020 18:34:56 +0000 (19:34 +0100)]
testing LD without ST

4 years agoOoops, forgot comparefixed.patch
Michael Nolan [Thu, 7 May 2020 18:21:07 +0000 (14:21 -0400)]
Ooops, forgot comparefixed.patch

4 years agoGet test_cmp working
Michael Nolan [Thu, 7 May 2020 18:18:32 +0000 (14:18 -0400)]
Get test_cmp working

4 years agoFix test_mtcrf. Test has been verified against qemu
Michael Nolan [Thu, 7 May 2020 18:13:24 +0000 (14:13 -0400)]
Fix test_mtcrf. Test has been verified against qemu

4 years agoMake FieldSelectableInt accept slices for set and get
Michael Nolan [Thu, 7 May 2020 17:44:33 +0000 (13:44 -0400)]
Make FieldSelectableInt accept slices for set and get

4 years agoAdd handling of add with comparison
Michael Nolan [Thu, 7 May 2020 15:40:31 +0000 (11:40 -0400)]
Add handling of add with comparison

4 years agoFix bug with comparisons in selectable_int.py
Michael Nolan [Thu, 7 May 2020 15:17:48 +0000 (11:17 -0400)]
Fix bug with comparisons in selectable_int.py

4 years agoAdd test_mfcr
Michael Nolan [Thu, 7 May 2020 14:37:20 +0000 (10:37 -0400)]
Add test_mfcr

4 years agocontinuing debugging of LD/ST CompUnit FSM and unit test
Luke Kenneth Casson Leighton [Thu, 7 May 2020 14:20:40 +0000 (15:20 +0100)]
continuing debugging of LD/ST CompUnit FSM and unit test

4 years agopartially-debugged ld/st comp unit using new PortInterface
Luke Kenneth Casson Leighton [Thu, 7 May 2020 12:48:33 +0000 (13:48 +0100)]
partially-debugged ld/st comp unit using new PortInterface

4 years agoRe-enable test_mtcrf
Michael Nolan [Wed, 6 May 2020 18:23:20 +0000 (14:23 -0400)]
Re-enable test_mtcrf

4 years agoAdd length helper for getting length of a selectable int
Michael Nolan [Wed, 6 May 2020 18:21:40 +0000 (14:21 -0400)]
Add length helper for getting length of a selectable int

4 years agoAdd helper functions to replace direct comparison in generated code
Michael Nolan [Wed, 6 May 2020 18:19:06 +0000 (14:19 -0400)]
Add helper functions to replace direct comparison in generated code

4 years agono syntax errors in LDSTCompUnit multi version
Luke Kenneth Casson Leighton [Wed, 6 May 2020 17:08:23 +0000 (18:08 +0100)]
no syntax errors in LDSTCompUnit multi version

4 years agoalmost complete LD/ST CompUnit, nearing testing
Luke Kenneth Casson Leighton [Wed, 6 May 2020 16:46:30 +0000 (17:46 +0100)]
almost complete LD/ST CompUnit, nearing testing

4 years agoLook up spr length from spr table
Michael Nolan [Wed, 6 May 2020 15:44:35 +0000 (11:44 -0400)]
Look up spr length from spr table

4 years agoAdd dict of spr properties to power_enums
Michael Nolan [Wed, 6 May 2020 15:42:23 +0000 (11:42 -0400)]
Add dict of spr properties to power_enums

4 years agoImplement bctr and mtspr
Michael Nolan [Wed, 6 May 2020 15:35:47 +0000 (11:35 -0400)]
Implement bctr and mtspr

4 years agoProperly implement LR and CTR
Michael Nolan [Wed, 6 May 2020 15:05:59 +0000 (11:05 -0400)]
Properly implement LR and CTR

4 years agoAdd ability to patch generated isa files
Michael Nolan [Wed, 6 May 2020 14:43:27 +0000 (10:43 -0400)]
Add ability to patch generated isa files

4 years agoSorta kinda working bl and blr - need to properly implement lr
Michael Nolan [Wed, 6 May 2020 14:32:24 +0000 (10:32 -0400)]
Sorta kinda working bl and blr - need to properly implement lr

4 years agoremove unneeded minerva code
Luke Kenneth Casson Leighton [Wed, 6 May 2020 12:34:28 +0000 (13:34 +0100)]
remove unneeded minerva code

4 years agomention need for DualPortSplitter class
Luke Kenneth Casson Leighton [Wed, 6 May 2020 12:26:24 +0000 (13:26 +0100)]
mention need for DualPortSplitter class

4 years agomore connecting signals for LDSTCompUnit according to diagram
Luke Kenneth Casson Leighton [Wed, 6 May 2020 10:55:45 +0000 (11:55 +0100)]
more connecting signals for LDSTCompUnit according to diagram

4 years agoupdate Makefile to include required build steps
Jacob Lifshay [Wed, 6 May 2020 00:55:05 +0000 (17:55 -0700)]
update Makefile to include required build steps

4 years agoAdd rudimentary branch capability
Michael Nolan [Tue, 5 May 2020 19:58:34 +0000 (15:58 -0400)]
Add rudimentary branch capability

4 years agoFix broken test_decoder_gas
Michael Nolan [Tue, 5 May 2020 18:40:46 +0000 (14:40 -0400)]
Fix broken test_decoder_gas

4 years agobegin connecting up signals for LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 5 May 2020 16:26:52 +0000 (17:26 +0100)]
begin connecting up signals for LDSTCompUnit

4 years agoMerge branch 'master' of git.libre-riscv.org:soc
Yehowshua Immanuel [Tue, 5 May 2020 14:21:10 +0000 (10:21 -0400)]
Merge branch 'master' of git.libre-riscv.org:soc

Removed named tuple duplicate - merging with Lukes commit.

4 years agoGit rid of named tuple imported twice
Yehowshua Immanuel [Tue, 5 May 2020 14:20:57 +0000 (10:20 -0400)]
Git rid of named tuple imported twice

4 years agonew version of LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 5 May 2020 14:12:57 +0000 (15:12 +0100)]
new version of LDSTCompUnit

4 years agoLink to documentation in README.md
Yehowshua Immanuel [Tue, 5 May 2020 14:06:40 +0000 (10:06 -0400)]
Link to documentation in README.md

4 years agocomments
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:53:13 +0000 (20:53 +0100)]
comments

4 years agotake out wait for busy in L0BufferCache tests
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:49:02 +0000 (20:49 +0100)]
take out wait for busy in L0BufferCache tests

4 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:41:53 +0000 (20:41 +0100)]
whitespace cleanup

4 years agobit of a mess, but functional. unit test passes on "basic" L0CacheBuffer
Luke Kenneth Casson Leighton [Mon, 4 May 2020 19:41:05 +0000 (20:41 +0100)]
bit of a mess, but functional.  unit test passes on "basic" L0CacheBuffer

4 years agohmmm trying to get st to acknowledge properly
Luke Kenneth Casson Leighton [Mon, 4 May 2020 17:59:51 +0000 (18:59 +0100)]
hmmm trying to get st to acknowledge properly

4 years agoadd links to bugreport and to memory/cache wiki page
Luke Kenneth Casson Leighton [Mon, 4 May 2020 17:27:23 +0000 (18:27 +0100)]
add links to bugreport and to memory/cache wiki page

4 years agoL0 cache/buffer first unit test, working except for one niggle
Luke Kenneth Casson Leighton [Mon, 4 May 2020 17:21:16 +0000 (18:21 +0100)]
L0 cache/buffer first unit test, working except for one niggle