soclayout.git
4 years agoadd experiment5
Luke Kenneth Casson Leighton [Tue, 25 Feb 2020 18:02:00 +0000 (18:02 +0000)]
add experiment5

4 years agoadd clk and ck so that ck is recognised for routing
Luke Kenneth Casson Leighton [Tue, 25 Feb 2020 17:57:59 +0000 (17:57 +0000)]
add clk and ck so that ck is recognised for routing

4 years agoadd make view
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 21:30:00 +0000 (21:30 +0000)]
add make view

4 years agobit more experimenting making an ioring around an adder
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 19:09:40 +0000 (19:09 +0000)]
bit more experimenting making an ioring around an adder

4 years agomake example as close to adder benchmark as possible
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 18:26:30 +0000 (18:26 +0000)]
make example as close to adder benchmark as possible

4 years agosimplify experiment4 to an adder, similar to adder benchmark
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 17:44:20 +0000 (17:44 +0000)]
simplify experiment4 to an adder, similar to adder benchmark

4 years agoadd mksyms.sh
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 17:07:57 +0000 (17:07 +0000)]
add mksyms.sh

4 years agowhoops yes use clocktree
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 13:19:58 +0000 (13:19 +0000)]
whoops yes use clocktree

4 years agoadd missing mksym.sh
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 11:13:34 +0000 (11:13 +0000)]
add missing mksym.sh

4 years agocontinue experimentation
Luke Kenneth Casson Leighton [Mon, 24 Feb 2020 11:07:24 +0000 (11:07 +0000)]
continue experimentation

4 years agoadd sm3 to nets
Luke Kenneth Casson Leighton [Sun, 23 Feb 2020 00:09:02 +0000 (00:09 +0000)]
add sm3 to nets

4 years agocorrect nets for experiment2
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 17:34:41 +0000 (17:34 +0000)]
correct nets for experiment2

4 years agotrack down module in which vdd / vss error exists (shift)
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 17:09:58 +0000 (17:09 +0000)]
track down module in which vdd / vss error exists (shift)

4 years agoremove working code, shrink "fail" case
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 16:57:53 +0000 (16:57 +0000)]
remove working code, shrink "fail" case

4 years agoadd test_partsig.py directly to experiment2
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 16:49:55 +0000 (16:49 +0000)]
add test_partsig.py directly to experiment2

4 years agoadd ioring experiment
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 15:07:06 +0000 (15:07 +0000)]
add ioring experiment

4 years agoadd sim just to see if anything happens
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 11:56:12 +0000 (11:56 +0000)]
add sim just to see if anything happens

4 years agomove Makefile3/4 to experiments3
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 11:35:29 +0000 (11:35 +0000)]
move Makefile3/4 to experiments3

4 years agomove part_sig_add to its own directory
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 11:30:41 +0000 (11:30 +0000)]
move part_sig_add to its own directory

4 years agomove alu_hier to own directory
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 11:28:38 +0000 (11:28 +0000)]
move alu_hier to own directory

4 years agochange coriolis settings, logmode true
Luke Kenneth Casson Leighton [Sat, 22 Feb 2020 11:25:49 +0000 (11:25 +0000)]
change coriolis settings, logmode true

4 years agoadd extra gitignores
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 20:00:01 +0000 (20:00 +0000)]
add extra gitignores

4 years agoadd path helpers sys libraries
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 19:53:59 +0000 (19:53 +0000)]
add path helpers sys libraries

4 years agoadd git ignore file
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 19:38:10 +0000 (19:38 +0000)]
add git ignore file

4 years agowrong script name
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 17:47:05 +0000 (17:47 +0000)]
wrong script name

4 years agoremove synthesise-yosys.mk use alliance one
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 14:56:51 +0000 (14:56 +0000)]
remove synthesise-yosys.mk use alliance one

4 years agoadd GND/PWR to see what happens in settings.py
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 13:08:15 +0000 (13:08 +0000)]
add GND/PWR to see what happens in settings.py

4 years agoreduce pmask to stop unconnected bits
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 13:05:30 +0000 (13:05 +0000)]
reduce pmask to stop unconnected bits

4 years agouse alternative experimental class TestAddMod2
Luke Kenneth Casson Leighton [Fri, 21 Feb 2020 12:39:20 +0000 (12:39 +0000)]
use alternative experimental class TestAddMod2

4 years agofix mask width
Luke Kenneth Casson Leighton [Thu, 20 Feb 2020 20:13:43 +0000 (20:13 +0000)]
fix mask width

4 years agoadd Makefile3
Luke Kenneth Casson Leighton [Thu, 20 Feb 2020 19:48:19 +0000 (19:48 +0000)]
add Makefile3

4 years agoadd second Makefile
Luke Kenneth Casson Leighton [Thu, 20 Feb 2020 18:59:06 +0000 (18:59 +0000)]
add second Makefile

4 years agomove part_sig_add name
Luke Kenneth Casson Leighton [Thu, 20 Feb 2020 17:27:10 +0000 (17:27 +0000)]
move part_sig_add name

4 years agorun alu_hier.py instead of alu.py (works)
Luke Kenneth Casson Leighton [Thu, 20 Feb 2020 00:23:00 +0000 (00:23 +0000)]
run alu_hier.py instead of alu.py (works)

4 years agoremove clock
Luke Kenneth Casson Leighton [Thu, 20 Feb 2020 00:21:03 +0000 (00:21 +0000)]
remove clock

4 years agoremove clock, use rename on clk in settings
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 23:08:30 +0000 (23:08 +0000)]
remove clock, use rename on clk in settings

4 years ago increase etesian, set clock to clk
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 23:08:01 +0000 (23:08 +0000)]
 increase etesian, set clock to clk

4 years agouse simpler alu rather than alu_hier
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 22:37:22 +0000 (22:37 +0000)]
use simpler alu rather than alu_hier

4 years agoadd clocks and reset and add alu.py as well
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 22:36:50 +0000 (22:36 +0000)]
add clocks and reset and add alu.py as well

4 years agoreplace part_sig_add with simpler design
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 21:48:45 +0000 (21:48 +0000)]
replace part_sig_add with simpler design

4 years agoadd alu_hier.py example
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 21:42:20 +0000 (21:42 +0000)]
add alu_hier.py example

4 years agoreplace VLOG with ILANG
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 21:38:58 +0000 (21:38 +0000)]
replace VLOG with ILANG

4 years agostart running and debugging
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 21:05:51 +0000 (21:05 +0000)]
start running and debugging

4 years agotry symlink to mk fragments
Luke Kenneth Casson Leighton [Wed, 19 Feb 2020 20:51:40 +0000 (20:51 +0000)]
try symlink to mk fragments

4 years agoremove whitespace
Luke Kenneth Casson Leighton [Sat, 15 Feb 2020 14:06:25 +0000 (14:06 +0000)]
remove whitespace

4 years agoyosys example makefile
Tobias Platen [Sat, 15 Feb 2020 13:33:39 +0000 (14:33 +0100)]
yosys example makefile

4 years agoadd synthesis-yosys.mk with ilang substituted
Luke Kenneth Casson Leighton [Fri, 14 Feb 2020 21:02:00 +0000 (21:02 +0000)]
add synthesis-yosys.mk with ilang substituted

4 years agofirst example code
Tobias Platen [Fri, 14 Feb 2020 16:30:44 +0000 (17:30 +0100)]
first example code

4 years agofirst empty commit
Luke Kenneth Casson Leighton [Tue, 11 Feb 2020 16:36:12 +0000 (16:36 +0000)]
first empty commit