Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 15:21:25 +0000 (16:21 +0100)]
write_entry, sef encoder.i has to be *conditional*
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 15:08:49 +0000 (16:08 +0100)]
sort-of put LFSR mode into SetAssocCache... not really sure what to do
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 12:53:47 +0000 (13:53 +0100)]
move max_exponent to be a property (max(self))
replace if tests with assert (single lines each)
remove self.max_exponent test on every element, use max(self) as property
set-ify the incoming argument exponents and add zero explicitly to it
pass that in to the set constructor, no need for accumulating in a temporary
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 12:34:53 +0000 (13:34 +0100)]
use a set not a list, can remove an extra line
also, spotted that width will always be 1 or greater
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 12:29:50 +0000 (13:29 +0100)]
simplify further,use max() on elements
remove function, use elements=[0] to accumulate exponents
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 11:14:42 +0000 (12:14 +0100)]
replace if elif elif with dictionary trick, and map-plus-lambda
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 11:09:31 +0000 (12:09 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 11:08:04 +0000 (12:08 +0100)]
add docstrings and comments
pass in LFSR_POLY_24 into example rather than the list
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:49:02 +0000 (11:49 +0100)]
skip the entire thing if width is zero
simplify creation of feedback: use Cat(feedback, statebits)
add test code-generation
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:31:30 +0000 (11:31 +0100)]
remove redundant Signal width=1
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:30:40 +0000 (11:30 +0100)]
remove property polynomial
(why assign __polynomial then add extra code where property polynomial
*returns* __polynomial? just... assign polynomial to self)
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:27:50 +0000 (11:27 +0100)]
LFSR2.pyi, type is set not frozenset, exponents returns list
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:26:00 +0000 (11:26 +0100)]
add error reports on exceptions in LFSR2
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:25:35 +0000 (11:25 +0100)]
use set instead of frozenset
return sorted list from exponents property
join operates on strings (not the list)
simplify __repr__
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:10:04 +0000 (11:10 +0100)]
use join trick instead of manually creating the exponent string
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 10:07:01 +0000 (11:07 +0100)]
instead of using abstract class Set, actually *derive* from frozenset
(which was not possible to do in python2): can remove 25% of LFSR2.py in
the process. also made max_exponent just a member of LFSR2 instead of
being a property (no need for __max_exponent when max_exponent is what
is needed and can be assigned then accessed directly)
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 09:58:28 +0000 (10:58 +0100)]
remove typing, move to .pyi file (increases code clarity)
Jacob Lifshay [Mon, 22 Apr 2019 07:47:08 +0000 (00:47 -0700)]
Merge remote-tracking branch 'origin/master'
Jacob Lifshay [Mon, 22 Apr 2019 07:46:45 +0000 (00:46 -0700)]
rename LFSR -> LFSR2
Jacob Lifshay [Mon, 22 Apr 2019 07:41:42 +0000 (00:41 -0700)]
add LFSR
Jacob Lifshay [Mon, 22 Apr 2019 07:40:04 +0000 (00:40 -0700)]
add empty __init__.py files
Jacob Lifshay [Mon, 22 Apr 2019 07:25:28 +0000 (00:25 -0700)]
add waveforms dir to git, ignoring all but .gitkeep
Daniel Benusovich [Mon, 22 Apr 2019 06:45:43 +0000 (23:45 -0700)]
Add lfsr with 11 bits
Jacob Lifshay [Mon, 22 Apr 2019 06:09:52 +0000 (23:09 -0700)]
add mypy typechecker integration
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 04:53:31 +0000 (05:53 +0100)]
make tag_valid and active_bit local
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 04:36:15 +0000 (05:36 +0100)]
disable write by default
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 04:28:54 +0000 (05:28 +0100)]
move setting up of tag into MemorySet
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:57:08 +0000 (04:57 +0100)]
add TODO comment, bug #71, replace PLRU with LFSR
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:52:09 +0000 (04:52 +0100)]
data_i needs to be data_size not input_size
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:44:35 +0000 (04:44 +0100)]
hmmm.... AddressEncoder needs to be of width way_count
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:44:15 +0000 (04:44 +0100)]
move tag/vector decoding into MemorySet
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:27:40 +0000 (04:27 +0100)]
data_size+tag_size = input_size, use it
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:18:23 +0000 (04:18 +0100)]
whoops, plru_array wasnt an array
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:18:04 +0000 (04:18 +0100)]
tidyup hit/multiple, move to main block
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 03:17:15 +0000 (04:17 +0100)]
tidy up comments
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 02:52:23 +0000 (03:52 +0100)]
small reorg, split memory into separate module with its own read/write ports
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 02:40:39 +0000 (03:40 +0100)]
same trick with encoder, remove switch, use encoder.o
Luke Kenneth Casson Leighton [Mon, 22 Apr 2019 02:33:57 +0000 (03:33 +0100)]
replace switch statement with straight index to array
Daniel Benusovich [Mon, 22 Apr 2019 01:24:07 +0000 (18:24 -0700)]
Add ubit test for set associative
Daniel Benusovich [Mon, 22 Apr 2019 01:23:54 +0000 (18:23 -0700)]
Use singal passed into plru rather than relying on internal signal
Daniel Benusovich [Mon, 22 Apr 2019 01:23:38 +0000 (18:23 -0700)]
Change plru to be combinational
Daniel Benusovich [Mon, 22 Apr 2019 01:19:34 +0000 (18:19 -0700)]
Add output signal to PLRU
Daniel Benusovich [Mon, 22 Apr 2019 00:37:55 +0000 (17:37 -0700)]
SAC seems to be working properly. Problems with PLRU are now the issue
Daniel Benusovich [Sun, 21 Apr 2019 23:36:04 +0000 (16:36 -0700)]
Remove LRU bits from memory
Daniel Benusovich [Sun, 21 Apr 2019 23:30:33 +0000 (16:30 -0700)]
Compilation success. Time for unit tests!
Daniel Benusovich [Sun, 21 Apr 2019 20:58:43 +0000 (13:58 -0700)]
Tryto make the cache compile. Not yet
Daniel Benusovich [Sun, 21 Apr 2019 20:45:56 +0000 (13:45 -0700)]
Add plru into set associative cache
Daniel Benusovich [Sun, 21 Apr 2019 20:45:41 +0000 (13:45 -0700)]
Add external access to table size to plru
Daniel Benusovich [Sun, 21 Apr 2019 19:29:10 +0000 (12:29 -0700)]
Make plru tree accessible from outside module for cache
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 13:06:51 +0000 (14:06 +0100)]
add in tlb_entries and asid_width parameters to constructors
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 09:18:27 +0000 (10:18 +0100)]
whoops, PTE bits wrong way round, make LSB to MSB
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 09:09:43 +0000 (10:09 +0100)]
correct mmu.py syntax errors, output ilang as a test
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 07:26:07 +0000 (08:26 +0100)]
comment where PermissionValidator needed
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 07:20:33 +0000 (08:20 +0100)]
begin experimental ariane mmu.sv conversion
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 06:43:35 +0000 (07:43 +0100)]
begin experimental ariane mmu.sv conversion
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 06:34:43 +0000 (07:34 +0100)]
begin experimental ariane mmu.sv conversion
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 06:04:54 +0000 (07:04 +0100)]
begin experimental ariane mmu.sv conversion
Luke Kenneth Casson Leighton [Sun, 21 Apr 2019 05:47:00 +0000 (06:47 +0100)]
add exception causes from ariane
Daniel Benusovich [Sun, 21 Apr 2019 01:07:00 +0000 (18:07 -0700)]
Tear out PLRU, TLBContent, TLBEntry into separate files
Daniel Benusovich [Sun, 21 Apr 2019 01:06:34 +0000 (18:06 -0700)]
Add tlb_content with TLBContent and TLBEntry classes
Daniel Benusovich [Sun, 21 Apr 2019 01:05:27 +0000 (18:05 -0700)]
Add PLRU file from tlb.py
Luke Kenneth Casson Leighton [Fri, 19 Apr 2019 07:31:30 +0000 (08:31 +0100)]
found linux kernel source references
Luke Kenneth Casson Leighton [Fri, 19 Apr 2019 07:18:34 +0000 (08:18 +0100)]
change indentation (combine some if/elifs)
Luke Kenneth Casson Leighton [Fri, 19 Apr 2019 07:06:17 +0000 (08:06 +0100)]
go back in vim undo history, recover itlb experimentation
Luke Kenneth Casson Leighton [Fri, 19 Apr 2019 01:42:20 +0000 (02:42 +0100)]
experimenting with PTW
Luke Kenneth Casson Leighton [Fri, 19 Apr 2019 01:05:01 +0000 (02:05 +0100)]
update comments
Luke Kenneth Casson Leighton [Thu, 18 Apr 2019 19:55:18 +0000 (20:55 +0100)]
random experiments with ptw.py
Luke Kenneth Casson Leighton [Thu, 18 Apr 2019 10:20:33 +0000 (11:20 +0100)]
use of plru starts to make sense, must set vpn == vaddr_i>>12
Luke Kenneth Casson Leighton [Thu, 18 Apr 2019 09:35:46 +0000 (10:35 +0100)]
add in name into plru to help debugging
Luke Kenneth Casson Leighton [Thu, 18 Apr 2019 09:33:06 +0000 (10:33 +0100)]
add in name into plru to help debugging
Luke Kenneth Casson Leighton [Thu, 18 Apr 2019 09:12:23 +0000 (10:12 +0100)]
continuing experimentation with PLRU
Luke Kenneth Casson Leighton [Thu, 18 Apr 2019 04:54:35 +0000 (05:54 +0100)]
add arbitrary random experimentation values for TLB and PTW unit tests
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 05:12:06 +0000 (06:12 +0100)]
tidyup
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 05:05:28 +0000 (06:05 +0100)]
move states to functions
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 04:49:45 +0000 (05:49 +0100)]
move idle state to separate function
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 04:46:53 +0000 (05:46 +0100)]
fix sync bug with tag_valid, simplify logic
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 04:30:54 +0000 (05:30 +0100)]
cleanup using temporaries
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 04:14:16 +0000 (05:14 +0100)]
simplify logic
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 04:04:47 +0000 (05:04 +0100)]
debug ptw.py
Luke Kenneth Casson Leighton [Mon, 15 Apr 2019 03:54:26 +0000 (04:54 +0100)]
debug ptw.py
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 17:53:16 +0000 (18:53 +0100)]
add comment
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 17:49:28 +0000 (18:49 +0100)]
move comments
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 17:47:16 +0000 (18:47 +0100)]
use Cat on list, makes graphviz clearer
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 17:29:49 +0000 (18:29 +0100)]
unsigned const
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 17:09:13 +0000 (18:09 +0100)]
tidyup comments
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 17:09:03 +0000 (18:09 +0100)]
content must be comb not sync
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 16:58:14 +0000 (17:58 +0100)]
comment spelling
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 16:50:12 +0000 (17:50 +0100)]
clarify output, use Cat on list
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 16:38:26 +0000 (17:38 +0100)]
rename _i and _o, for clarity: replace_en comb not sync
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 16:18:35 +0000 (17:18 +0100)]
redundant argument lu_hit
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 16:13:11 +0000 (17:13 +0100)]
split out into modules
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 15:36:13 +0000 (16:36 +0100)]
split into separate module instead of array
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 14:07:28 +0000 (15:07 +0100)]
update comment block
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 14:07:13 +0000 (15:07 +0100)]
update comment block
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 14:01:58 +0000 (15:01 +0100)]
create flatten and use in eq
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 12:51:58 +0000 (13:51 +0100)]
temporary signals, efforts to simplify graph
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 12:32:56 +0000 (13:32 +0100)]
add in temporaries, get graphviz down in size
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 12:18:16 +0000 (13:18 +0100)]
work towards getting PTW translation working
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 11:57:49 +0000 (12:57 +0100)]
correct python syntax errors
Luke Kenneth Casson Leighton [Sun, 14 Apr 2019 11:40:04 +0000 (12:40 +0100)]
update comments