mesa.git
5 years agopanfrost/midgard: Add umin/umax opcodes
Alyssa Rosenzweig [Fri, 5 Apr 2019 05:16:54 +0000 (05:16 +0000)]
panfrost/midgard: Add umin/umax opcodes

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Add tilebuffer load? branch
Alyssa Rosenzweig [Fri, 5 Apr 2019 05:16:32 +0000 (05:16 +0000)]
panfrost: Add tilebuffer load? branch

Also document branches better.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/decode: Add flags for tilebuffer readback
Alyssa Rosenzweig [Fri, 5 Apr 2019 01:17:21 +0000 (01:17 +0000)]
panfrost/decode: Add flags for tilebuffer readback

These flags are set when reading back the tilebuffer from a fragment
shader via various mechanisms (including ARM_shader_framebuffer_fetch
and EXT_pixel_local_storage).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: use nir_src_is_const and nir_src_as_uint
Karol Herbst [Fri, 29 Mar 2019 20:40:45 +0000 (21:40 +0100)]
panfrost/midgard: use nir_src_is_const and nir_src_as_uint

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agovc4: Prefer nir_src_comp_as_uint over nir_src_as_const_value
Jason Ekstrand [Tue, 2 Apr 2019 02:23:01 +0000 (21:23 -0500)]
vc4: Prefer nir_src_comp_as_uint over nir_src_as_const_value

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agov3d: prefer using nir_src_comp_as_int over nir_src_as_const_value
Karol Herbst [Thu, 28 Mar 2019 16:53:30 +0000 (17:53 +0100)]
v3d: prefer using nir_src_comp_as_int over nir_src_as_const_value

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogallium/util: Add const to u_range_intersect
Kenneth Graunke [Fri, 5 Apr 2019 18:52:59 +0000 (11:52 -0700)]
gallium/util: Add const to u_range_intersect

This doesn't modify the range, so it can accept a const pointer.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agogallium/hud: add CPU usage support for FreeBSD
Greg V [Sun, 3 Mar 2019 15:40:58 +0000 (18:40 +0300)]
gallium/hud: add CPU usage support for FreeBSD

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoiris: Silence unused variable warnings in release mode
Kenneth Graunke [Sat, 6 Apr 2019 22:57:35 +0000 (15:57 -0700)]
iris: Silence unused variable warnings in release mode

5 years agonir/algebraic: Add some logical OR and AND patterns
Jason Ekstrand [Fri, 29 Mar 2019 22:12:47 +0000 (17:12 -0500)]
nir/algebraic: Add some logical OR and AND patterns

The new OR pattern has been seen in the wild and can end up being
generated by GLSLang.  Not sure about the other two new patterns but we
may as well throw them in for completeness.  While we're here, we can
drop the '@bool' specifier from the one pattern because specifying True
already implies 1-bit which basically implies boolean.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15321227 -> 15321129 (<.01%)
    instructions in affected programs: 3594 -> 3496 (-2.73%)
    helped: 6
    HURT: 0

    total cycles in shared programs: 357481321 -> 357479725 (<.01%)
    cycles in affected programs: 44109 -> 42513 (-3.62%)
    helped: 6
    HURT: 0

VkPipeline-DB results on Kaby Lake:

    total instructions in shared programs: 3770504 -> 3769734 (-0.02%)
    instructions in affected programs: 19058 -> 18288 (-4.04%)
    helped: 163
    HURT: 0

    total cycles in shared programs: 1417583701 -> 1417569727 (<.01%)
    cycles in affected programs: 750958 -> 736984 (-1.86%)
    helped: 158
    HURT: 1

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agonir/algebraic: Drop some @bool specifiers
Jason Ekstrand [Sat, 30 Mar 2019 03:51:20 +0000 (22:51 -0500)]
nir/algebraic: Drop some @bool specifiers

Now that we have one-bit booleans, we don't need to rely on looking at
parent instructions in order to figure out if a value is a Boolean most
of the time.  We can drop these specifiers and now the optimizations
will apply more generally.

Shader-DB results on Kaby Lake:

    total instructions in shared programs: 15321168 -> 15321227 (<.01%)
    instructions in affected programs: 8836 -> 8895 (0.67%)
    helped: 1
    HURT: 31

    total cycles in shared programs: 357481781 -> 357481321 (<.01%)
    cycles in affected programs: 146524 -> 146064 (-0.31%)
    helped: 22
    HURT: 10

    total spills in shared programs: 23675 -> 23673 (<.01%)
    spills in affected programs: 11 -> 9 (-18.18%)
    helped: 1
    HURT: 0

    total fills in shared programs: 32040 -> 32036 (-0.01%)
    fills in affected programs: 27 -> 23 (-14.81%)
    helped: 1
    HURT: 0

No change in VkPipeline-DB

Looking at the instructions hurt, a bunch of them seem to be a case
where doing exactly the right thing in NIR ends up doing the wrong-ish
thing in the back-end because flags are dumb.  In particular, there's a
case where we have a MUL followed by a CMP followed by a SEL and when we
turn that SEL into an OR, it uses the GRF result of the CMP rather than
the flag result so the CMP can't be merged with the MUL.  Those shaders
appear to schedule better according to the cycle estimates so I guess
it's a win?  Also it helps spilling in one Car Chase compute shader.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoutil: clean the 24-bit unused field to avoid an issues
Andrii Simiklit [Wed, 3 Apr 2019 13:51:14 +0000 (16:51 +0300)]
util: clean the 24-bit unused field to avoid an issues

This is a field of FLOAT_32_UNSIGNED_INT_24_8_REV texture pixel.
OpenGL spec "8.4.4.2 Special Interpretations" is saying:
   "the second word contains a packed 24-bit unused field,
    followed by an 8-bit index"
The spec doesn't require us to clear this unused field
however it make sense to do it to avoid some
undefined behavior in some apps.

Suggested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110305
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
5 years agonir: Take if_uses into account when repairing SSA
Caio Marcelo de Oliveira Filho [Thu, 4 Apr 2019 19:46:42 +0000 (12:46 -0700)]
nir: Take if_uses into account when repairing SSA

If a def is used as an condition before its definition, we should also
consider this a case to repair.  When repairing, make sure we rewrite
any if conditions too.

Found in while inspecting a SPIR-V conversion from a 'continue block'
that contains a conditional branch.  We pull the continue block up to
the beggining of the loop, and the condition in the branch ends up
defined afterwards.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 364212f1ede4b "nir: Add a pass to repair SSA form"
5 years agotegra: fix the build after the set_shader_buffers change
Marek Olšák [Fri, 5 Apr 2019 15:18:21 +0000 (11:18 -0400)]
tegra: fix the build after the set_shader_buffers change

5 years agogallium/auxiliary/vl: Add barrier/unbind after compute shader launch.
James Zhu [Fri, 29 Mar 2019 19:59:39 +0000 (15:59 -0400)]
gallium/auxiliary/vl: Add barrier/unbind after compute shader launch.

Add memory barrier sync for multiple launch cases, and unbind completed
resources after launch.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/auxiliary/vl: Fixed blank issue with compute shader
James Zhu [Fri, 29 Mar 2019 19:57:51 +0000 (15:57 -0400)]
gallium/auxiliary/vl: Fixed blank issue with compute shader

Multiple init buffer within one open instance will cause blank issue.
Updating viewport per frame will fix this issue.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/auxiliary/vl: Fixed blur issue with weave compute shader
James Zhu [Tue, 19 Mar 2019 19:45:29 +0000 (15:45 -0400)]
gallium/auxiliary/vl: Fixed blur issue with weave compute shader

Correct wrong interpolatation with top/bottom row which caused blur issue.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Tested-by: Bruno Milreu <bmilreu@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agodocs: update calendar, add news item and link release notes for 18.3.6
Emil Velikov [Fri, 5 Apr 2019 12:24:29 +0000 (13:24 +0100)]
docs: update calendar, add news item and link release notes for 18.3.6

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
5 years agodocs: add sha256 checksums for 18.3.6
Emil Velikov [Fri, 5 Apr 2019 11:00:12 +0000 (12:00 +0100)]
docs: add sha256 checksums for 18.3.6

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit eb9da68cbf23aafb1192beed084b2f05df65dd04)

5 years agodocs: add release notes for 18.3.6
Emil Velikov [Fri, 5 Apr 2019 10:59:15 +0000 (11:59 +0100)]
docs: add release notes for 18.3.6

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit b03f51c4b4dfa54775e866b75f68a41862c062c2)

5 years agonir: do not pack varying with different types
Samuel Pitoiset [Fri, 5 Apr 2019 09:26:12 +0000 (11:26 +0200)]
nir: do not pack varying with different types

The current algorithm only supports packing 32-bit types.
If a shader uses both 16-bit and 32-bit varyings, we shouldn't
compact them together.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agosoftpipe: Use mag texture filter also for clamped lod == 0
Gert Wollny [Thu, 4 Apr 2019 09:34:26 +0000 (11:34 +0200)]
softpipe: Use mag texture filter also for clamped lod == 0

Follow the spec when selecting the magnification filter (OpenGL 4.5,
section 8.14):

  If λ(x, y) is less than or equal to the constant c (see section 8.15)
  the texture is said to be magnified;

While we're here also silence a potential warning about implicit float
to double conversion.

v2: Update commit message to contain a reference to the spec as pointed
    out by Eric.

Fixes a number of dEQP GLES2 and GLES3 test out of:
 dEQP-GLES2.functional.texture.filtering.*
 dEQP-GLES2.functional.texture.vertex.2d.filtering.*
 dEQP-GLES3.functional.texture.vertex.*.filtering.*
 dEQP-GLES3.functional.texture.filtering.*
 dEQP-GLES3.functional.texture.shadow.2d.*

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoiris: handle aux properly in iris_resource_get_handle
Tapani Pälli [Fri, 5 Apr 2019 05:55:18 +0000 (08:55 +0300)]
iris: handle aux properly in iris_resource_get_handle

Disable aux when resource seen the first time and EXPLICIT_FLUSH
not being set. This fixes issues seen when launching Xorg and
CCS_E getting utilized.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agov3d: Add some more new packets for V3D 4.x.
Eric Anholt [Thu, 4 Apr 2019 17:51:22 +0000 (10:51 -0700)]
v3d: Add some more new packets for V3D 4.x.

The T/G shader references and common state will be needed for GLES 3.2.

5 years agov3d: Don't try to use the TFU blit path if a scissor is enabled.
Eric Anholt [Wed, 3 Apr 2019 19:39:54 +0000 (12:39 -0700)]
v3d: Don't try to use the TFU blit path if a scissor is enabled.

We'll need to do a render-based blit for scissors, since the TFU (as seen
in this conditional) can only update a whole surface.

Fixes: 976ea90bdca2 ("v3d: Add support for using the TFU to do some blits.")
Fixes piglit fbo-scissor-blit.

5 years agov3d: Bump the maximum texture size to 4k for V3D 4.x.
Eric Anholt [Fri, 29 Mar 2019 22:38:15 +0000 (15:38 -0700)]
v3d: Bump the maximum texture size to 4k for V3D 4.x.

4.1 and 4.2 both have the same 16k limit, but it I'm seeing GPU hangs in
the CTS at 8k and 16k.  4k at least lets us get one 4k display working.

Cc: mesa-stable@lists.freedesktop.org
5 years agov3d: Add support for handling OOM signals from the simulator.
Eric Anholt [Tue, 2 Apr 2019 23:51:44 +0000 (16:51 -0700)]
v3d: Add support for handling OOM signals from the simulator.

I have v3d allocating enough initial allocation memory that we've been
passing tests without it, but to match kernel behavior more it would be
good to actually exercise the OOM path.

5 years agomesa/main: Fix multisample texture initialize
Illia Iorin [Thu, 28 Feb 2019 10:33:50 +0000 (12:33 +0200)]
mesa/main: Fix multisample texture initialize

Sampler of Multisample textures wasn't initialized correct. So when
texture object created as  multisample its sampler is initialized in a
individual case. We change the initial state of TEXTURE_MIN_FILTER and
TEXTURE_MAG_FILTER to NEAREST.
These changes are approved by KhronosGroup.
https://github.com/KhronosGroup/OpenGL-API/issues/45

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Signed-off-by: Illia Iorin <illia.iorin@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109057

5 years agoglsl: Fix input/output structure matching across shader stages
Sergii Romantsov [Thu, 24 Jan 2019 12:33:55 +0000 (14:33 +0200)]
glsl: Fix input/output structure matching across shader stages

Section 7.4.1 (Shader Interface Matching) of the OpenGL 4.30 spec says:

    "Variables or block members declared as structures are considered
     to match in type if and only if structure members match in name,
     type, qualification, and declaration order."

Fixes:
     * layout-location-struct.shader_test

v2: rebased against master and small fixes

Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108250

5 years agoddebug: add compute functions to help hang detection
Dave Airlie [Fri, 29 Mar 2019 02:57:55 +0000 (12:57 +1000)]
ddebug: add compute functions to help hang detection

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoiris: avoid use after free in shader destruction
Dave Airlie [Thu, 4 Apr 2019 01:18:26 +0000 (11:18 +1000)]
iris: avoid use after free in shader destruction

While playing with compute shaders, I was getting a random crash,
noticed that bind_state was using the old shader info for comparision,
but gallium allows the shader to be deleted while bound, so this could
lead to a use after free.

This can't happen using the cso cache. As it tracks all of this.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoradeonsi: set exact shader buffer read/write usage in CS
Marek Olšák [Thu, 28 Feb 2019 18:02:13 +0000 (13:02 -0500)]
radeonsi: set exact shader buffer read/write usage in CS

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoglsl: remember which SSBOs are not read-only and pass it to gallium
Marek Olšák [Wed, 3 Apr 2019 18:22:16 +0000 (14:22 -0400)]
glsl: remember which SSBOs are not read-only and pass it to gallium

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agogallium: add writable_bitmask parameter into set_shader_buffers
Marek Olšák [Thu, 28 Feb 2019 02:54:47 +0000 (21:54 -0500)]
gallium: add writable_bitmask parameter into set_shader_buffers

to indicate write usage per buffer.
This is just a hint (it will be used by radeonsi).

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agoiris: Fix assert when using vertex attrib without buffer binding
Danylo Piliaiev [Thu, 4 Apr 2019 12:04:50 +0000 (15:04 +0300)]
iris: Fix assert when using vertex attrib without buffer binding

The GL 4.5 spec says:
 "If any enabled array’s buffer binding is zero when DrawArrays or
  one of the other drawing commands defined in section 10.4 is called,
  the result is undefined."

The result is undefined but it should not crash.

Fixes: gl-3.1-vao-broken-attrib
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: move iris_flush_resource so we can call it from get_handle
Tapani Pälli [Thu, 28 Mar 2019 08:49:45 +0000 (10:49 +0200)]
iris: move iris_flush_resource so we can call it from get_handle

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Save/restore MI_PREDICATE_RESULT, not MI_PREDICATE_DATA.
Kenneth Graunke [Tue, 2 Apr 2019 06:28:06 +0000 (23:28 -0700)]
iris: Save/restore MI_PREDICATE_RESULT, not MI_PREDICATE_DATA.

MI_PREDICATE_DATA is an intermediate storage for the MI_PREDICATE
command's calculations - it holds the result of the subtraction when
the compare operation is SRCS_EQUAL or DELTAS_EQUAL.  But the actual
result of the predication is MI_PREDICATE_RESULT, which is what we
want to copy from the render context to the compute context.

5 years agoutil/process: document memory leak
Eric Engestrom [Fri, 22 Mar 2019 16:54:57 +0000 (16:54 +0000)]
util/process: document memory leak

We consider it acceptable, but let's still document it in case people
notice it and are not sure why it's there.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
5 years agosimplify LLVM version string printing
Eric Engestrom [Thu, 14 Mar 2019 13:58:54 +0000 (13:58 +0000)]
simplify LLVM version string printing

Figure it out once in the build system, then just use that all over the place.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/u_dump: util_dump_sampler_view: Dump u.tex.first_level
Guido Günther [Wed, 3 Apr 2019 16:13:49 +0000 (18:13 +0200)]
gallium/u_dump: util_dump_sampler_view: Dump u.tex.first_level

Dump u.tex.first_level instead of dumping u.tex.last_level twice.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium: ddebug: Add missing fence related wrappers
Guido Günther [Wed, 3 Apr 2019 11:08:47 +0000 (13:08 +0200)]
gallium: ddebug: Add missing fence related wrappers

Without that `GALLIUM_DDEBUG=always kmscube -A` would segfault like

  #0  0x0000000000000000 in  ()
  #1  0x0000ffffa72a3c54 in dri2_get_fence_fd (_screen=0xaaaaed4f2090, _fence=0xaaaaed9ef880) at ../src/gallium/state_trackers/dri/dri_helpers.c:140
  #2  0x0000ffffa8744824 in dri2_dup_native_fence_fd (drv=0xaaaaed5010c0, disp=0xaaaaed5029a0, sync=0xaaaaed9ef7c0) at ../src/egl/drivers/dri2/egl_dri2.c:3050
  #3  0x0000ffffa87339b8 in eglDupNativeFenceFDANDROID (dpy=0xaaaaed5029a0, sync=0xaaaaed9ef7c0) at ../src/egl/main/eglapi.c:2107
  #4  0x0000aaaabd29ca90 in  ()
  #5  0x0000aaaabd401000 in  ()

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
5 years agost/mesa: Fix GL_MAP_COLOR with glDrawPixels GL_COLOR_INDEX
Danylo Piliaiev [Wed, 3 Apr 2019 15:09:24 +0000 (18:09 +0300)]
st/mesa: Fix GL_MAP_COLOR with glDrawPixels GL_COLOR_INDEX

Documentation for glDrawPixels with GL_COLOR_INDEX says:
 "If the GL is in color index mode, and if GL_MAP_COLOR is true,
  the index is replaced with the value that it references in
  lookup table GL_PIXEL_MAP_I_TO_I"

We are always in RGBA mode and there is nothing in documentation
about GL_MAP_COLOR in RGBA mode for GL_COLOR_INDEX.

Scale and bias are also only applicable for RGBA format and not
mentioned for GL_COLOR_INDEX.

Thus the behaviour will be on par with i965.

Fixes: gl-1.0-drawpixels-color-index
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/hud: fix rounding error in nic bps computation
Eric Engestrom [Tue, 19 Mar 2019 14:15:35 +0000 (14:15 +0000)]
gallium/hud: fix rounding error in nic bps computation

While at it, fix typo in "rounding error" :P

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/hud: prevent buffer overflow
Eric Engestrom [Tue, 19 Mar 2019 14:11:48 +0000 (14:11 +0000)]
gallium/hud: prevent buffer overflow

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/hud: fix memory leaks
Eric Engestrom [Tue, 19 Mar 2019 14:11:09 +0000 (14:11 +0000)]
gallium/hud: fix memory leaks

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi: enable displayable DCC on Ravens
Marek Olšák [Wed, 9 Jan 2019 01:08:08 +0000 (20:08 -0500)]
radeonsi: enable displayable DCC on Ravens

5 years agoradeonsi: add support for displayable DCC for multi-RB chips
Marek Olšák [Sat, 5 Jan 2019 00:39:01 +0000 (19:39 -0500)]
radeonsi: add support for displayable DCC for multi-RB chips

A compute shader is used to reorder DCC data from aligned to unaligned.

5 years agoradeonsi: add support for displayable DCC for 1 RB chips
Marek Olšák [Sat, 5 Jan 2019 00:19:54 +0000 (19:19 -0500)]
radeonsi: add support for displayable DCC for 1 RB chips

This is the simpler codepath - just disable RB and pipe alignment for DCC.

5 years agoradeonsi: add ability to bind images as image buffers
Marek Olšák [Sat, 5 Jan 2019 00:27:27 +0000 (19:27 -0500)]
radeonsi: add ability to bind images as image buffers

so that we can bind DCC (texture) as an image buffer.

5 years agoradeonsi/gfx9: add support for PIPE_ALIGNED=0
Marek Olšák [Fri, 9 Nov 2018 21:51:47 +0000 (16:51 -0500)]
radeonsi/gfx9: add support for PIPE_ALIGNED=0

Needed by displayable DCC.

We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.

5 years agoamd/addrlib: fix uninitialized values for Addr2ComputeDccAddrFromCoord
Marek Olšák [Wed, 3 Apr 2019 21:17:08 +0000 (17:17 -0400)]
amd/addrlib: fix uninitialized values for Addr2ComputeDccAddrFromCoord

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoiris: move variable to the scope where it is being used
Tapani Pälli [Tue, 2 Apr 2019 06:12:21 +0000 (09:12 +0300)]
iris: move variable to the scope where it is being used

iris_upload_border_color is passed a pointer which points to
variable that is introduced in a different scope.

CID: 1444296
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agost/nir: run st_nir_opts after 64bit ops lowering
Tapani Pälli [Tue, 2 Apr 2019 05:56:07 +0000 (08:56 +0300)]
st/nir: run st_nir_opts after 64bit ops lowering

CID: 1444309
Fixes: 9ab1b1d0227 "st/nir: Move 64-bit lowering later"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agopanfrost: Size tiled temp buffers correctly
Alyssa Rosenzweig [Wed, 3 Apr 2019 03:52:36 +0000 (03:52 +0000)]
panfrost: Size tiled temp buffers correctly

This should lower transient memory usage and improve performance
slightly (due to less memory to malloc/free, better cache locality,
etc).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Respect box->width in tiled stores
Alyssa Rosenzweig [Wed, 3 Apr 2019 03:36:38 +0000 (03:36 +0000)]
panfrost: Respect box->width in tiled stores

This fixes a regression uploading partial tiled textures introduced
sometime during the cubemap series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Cleanup some indirection in pan_resource
Alyssa Rosenzweig [Wed, 3 Apr 2019 02:15:18 +0000 (02:15 +0000)]
panfrost: Cleanup some indirection in pan_resource

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Implement system values
Alyssa Rosenzweig [Wed, 3 Apr 2019 01:48:09 +0000 (01:48 +0000)]
panfrost: Implement system values

This patch implements system values via specially-crafted uniforms.
While we previously had an ad hoc system for passing the viewport into
the vertex shader, this commit generalizes the system to allow for
arbitrary system values to be added to both shader stages. While we're
at it, we clean up uniform handling code (which was considerably muddied
to handle the ad hoc viewport uniform).

This commit serves as both a cleanup of the existing codebase and the
precursor to new functionality, like implementing textureSize().

Concurrent with these changes is respecting the depth transform, which
was not possible with the old fixed uniform system and here serves as a
proof-of-correctness test (as well as justifying the NIR changes).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agonir: Add "viewport vector" system values
Alyssa Rosenzweig [Wed, 3 Apr 2019 01:45:44 +0000 (01:45 +0000)]
nir: Add "viewport vector" system values

While a partial set of viewport system values exist, these are scalar
values, which is a poor fit for viewport transformations on vector ISAs
like Midgard (where the vec3 values for scale and offset each need to be
coherent in a vec4 uniform slot to take advantage of vectorized
transform math). This patch adds vec3 scale/offset fields corresponding
to the 3D Gallium viewport / glViewport+depth

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agovirgl: also destroy all read-transfers
Erik Faye-Lund [Tue, 2 Apr 2019 08:48:30 +0000 (10:48 +0200)]
virgl: also destroy all read-transfers

For texture write-transfers, we either free them on the transfer-queue
or right away. But for read-transfers, we currently only destroy them in
case they used a temp-resource. This leads to occasional resource-leaks.

Let's add a call to virgl_resource_destroy_transfer in the missing case.

Do the same thing for buffers as well, but the logic is a bit easier to
follow there.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: f0e71b10888 ("virgl: use transfer queue")
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agomeson: Error if LLVM is turned off but clover it turned on
Dylan Baker [Mon, 1 Apr 2019 17:14:54 +0000 (10:14 -0700)]
meson: Error if LLVM is turned off but clover it turned on

Since clover has a hard requirement on LLVM

v2: - make error message more specific

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agomeson: Error if LLVM doesn't have rtti when building clover
Dylan Baker [Mon, 1 Apr 2019 17:12:03 +0000 (10:12 -0700)]
meson: Error if LLVM doesn't have rtti when building clover

We already do this for nouveau, but it's required for clover too.

5 years agopanfrost: Remove support for legacy kernels
Alyssa Rosenzweig [Sun, 31 Mar 2019 19:06:05 +0000 (19:06 +0000)]
panfrost: Remove support for legacy kernels

Previously, there was minimal support for interoperating with legacy
kernels (reusing kernel modules originally designed for proprietary
legacy userspaces, rather than for upstream-friendly free software
stacks). Now that the Panfrost kernel is stabilising, this commit drops
the legacy code path.

Panfrost users need to use a modern, mainline kernel supporting the
Panfrost kernel driver from this commit forward.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
5 years agoetnaviv: only try to construct scanout resource when on KMS winsys
Lucas Stach [Wed, 27 Mar 2019 11:25:18 +0000 (12:25 +0100)]
etnaviv: only try to construct scanout resource when on KMS winsys

Trying to construct a scanout capable buffer will only ever work when
when we are on top of a KMS winsys, as the render node isn't capable
of allocating contiguous buffers.

Tested-by: Marius Vlad <marius.vlad@collabora.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
5 years agoetnaviv: flush all pending contexts when accessing a resource with the CPU
Lucas Stach [Wed, 27 Mar 2019 11:22:58 +0000 (12:22 +0100)]
etnaviv: flush all pending contexts when accessing a resource with the CPU

When setting up a transfer to a resource, all contexts where the resource
is pending must be flushed. Otherwise a write transfer might be started
in the current context before all contexts that access the resource in
shared (read) mode have been executed.

Fixes: 64813541d575 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-By: Guido Günther <agx@sigxcpu.org>
5 years agoetnaviv: don't flush own context when updating resource use
Lucas Stach [Wed, 27 Mar 2019 11:22:57 +0000 (12:22 +0100)]
etnaviv: don't flush own context when updating resource use

The context is self synchronizing at the GPU side, as commands are
executed in order. We must not flush our own context when updating the
resource use, as that leads to excessive flushing on effectively every
draw call, causing huge CPU overhead.

Fixes: 64813541d575 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
5 years agoetnaviv: shrink struct etna_3d_state
Christian Gmeiner [Wed, 27 Mar 2019 13:58:16 +0000 (14:58 +0100)]
etnaviv: shrink struct etna_3d_state

Drop struct members which are only written to but never read from.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
5 years agointel/compiler: use defined size for vector components
Dave Airlie [Wed, 3 Apr 2019 02:20:40 +0000 (12:20 +1000)]
intel/compiler: use defined size for vector components

If we increase vector sizing later it would be nice to avoid
tripped over this again.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agonir: use proper array sizing define for vectors
Dave Airlie [Wed, 3 Apr 2019 02:20:02 +0000 (12:20 +1000)]
nir: use proper array sizing define for vectors

If we increase the vector size in the future it would be good
to not have to fix these up, this should change nothing at present.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agoRevert "nir: propagate known constant values into the if-then branch"
Timothy Arceri [Wed, 3 Apr 2019 02:24:18 +0000 (13:24 +1100)]
Revert "nir: propagate known constant values into the if-then branch"

This reverts commit 4218b6422cf1ff70c7f0feeec699a35e88522ed7.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110311

5 years agonir: propagate known constant values into the if-then branch
Timothy Arceri [Fri, 23 Nov 2018 00:49:19 +0000 (11:49 +1100)]
nir: propagate known constant values into the if-then branch

Helps Max Waves / VGPR use in a bunch of Unigine Heaven
shaders.

shader-db results radeonsi (VEGA):
Totals from affected shaders:
SGPRS: 5505440 -> 5505872 (0.01 %)
VGPRS: 3077520 -> 3077296 (-0.01 %)
Spilled SGPRs: 39032 -> 39030 (-0.01 %)
Spilled VGPRs: 16326 -> 16326 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 744 -> 744 (0.00 %) dwords per thread
Code Size: 123755028 -> 123753316 (-0.00 %) bytes
Compile Time: 2751028 -> 2560786 (-6.92 %) milliseconds
LDS: 1415 -> 1415 (0.00 %) blocks
Max Waves: 972192 -> 972240 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

vkpipeline-db results RADV (VEGA):

Totals from affected shaders:
SGPRS: 160 -> 160 (0.00 %)
VGPRS: 88 -> 88 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 18268 -> 18152 (-0.63 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 26 -> 26 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agovirgl: close drm fd when destroying virgl screen.
Lepton Wu [Mon, 18 Mar 2019 23:40:25 +0000 (16:40 -0700)]
virgl: close drm fd when destroying virgl screen.

This fd was create in virgl_drm_screen_create and should be closed
in virgl_drm_screen_destroy.

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
5 years agoiris: Enable fast clears on gen8.
Rafael Antognolli [Tue, 26 Mar 2019 22:35:00 +0000 (15:35 -0700)]
iris: Enable fast clears on gen8.

Since we are now properly storing the clear color with SCS bits, we can
now enable fast clears on gen8 too.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Add aux.sampler_usages.
Rafael Antognolli [Wed, 27 Mar 2019 21:42:12 +0000 (14:42 -0700)]
iris: Add aux.sampler_usages.

We want to skip some types of aux usages (for instance,
ISL_AUX_USAGE_HIZ when the hardware doesn't support it, or when we have
multisampling) when sampling from the surface.

Instead of checking for those cases while filling the surface state and
leaving it blank, let's have a version of aux.possible_usages for
sampling. This way we can also avoid allocating surface state for the
cases we don't use.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Do not allocate clear_color_bo for gen8.
Rafael Antognolli [Tue, 26 Mar 2019 23:28:10 +0000 (16:28 -0700)]
iris: Do not allocate clear_color_bo for gen8.

Since we are not using it for the clear color, there's no need to
allocate it.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Manually apply fast clear color channel overrides.
Rafael Antognolli [Wed, 27 Mar 2019 17:27:18 +0000 (10:27 -0700)]
iris: Manually apply fast clear color channel overrides.

At the fast clear time, the only swizzle we have available is actually
the identity swizzle (which we use for most rendering). So the call to
swizzle_color_value() becomes simply a no-op, and doesn't properly zero
out the unused channels.

We have to manually override those channels.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris/gen8: Re-emit the SURFACE_STATE if the clear color changed.
Rafael Antognolli [Wed, 27 Mar 2019 20:09:34 +0000 (13:09 -0700)]
iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.

The swizzle for rendering surfaces is always identity. So when we are
doing the fast clear, we don't have enough information to store the
clear color OR'ed with the Shader Channel Select bits for the dword in
the SURFACE_STATE.

Instead of trying to patch up the SURFACE_STATE correctly later, by
reading the color from the clear color state buffer and then doing all
the operations to store it, let's just re-emit the whole SURFACE_STATE.
That should make things way simpler on gen8, and we can still use the
clear color state buffer for gen9+.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Only update clear color for gens 8 and 9.
Rafael Antognolli [Tue, 26 Mar 2019 18:08:22 +0000 (11:08 -0700)]
iris: Only update clear color for gens 8 and 9.

Newer gens can read it directly.

Also properly skip updating the ISL_AUX_USAGE_NONE surface.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agohaiku: Fix hgl dispatch build. Tested under meson/scons.
Alexander von Gluck IV [Sun, 31 Mar 2019 00:15:40 +0000 (00:15 +0000)]
haiku: Fix hgl dispatch build. Tested under meson/scons.

Reviewed-by: Brian Paul <brianp@vmware.com>
5 years agodocs: Fix 19.0.x version numbers
Guido Günther [Mon, 1 Apr 2019 15:58:24 +0000 (17:58 +0200)]
docs: Fix 19.0.x version numbers

The list has 19.0.2 twice.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
5 years agodocs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0
Marek Olšák [Tue, 2 Apr 2019 14:47:37 +0000 (10:47 -0400)]
docs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0

5 years agoCI: use wayland ci-templates repo to create the base image
Benjamin Tissoires [Tue, 2 Apr 2019 07:24:00 +0000 (09:24 +0200)]
CI: use wayland ci-templates repo to create the base image

There shouldn't be a difference for users, but this way we do manage
all of our containers from freedesktop.org

note: compared to the provious Dockerfile, we need to manually
      add gcc, g++ and python*-wheel

Signed-off-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoradeonsi: don't use PFP_SYNC_ME with compute-only contexts
Marek Olšák [Mon, 1 Apr 2019 16:29:43 +0000 (12:29 -0400)]
radeonsi: don't use PFP_SYNC_ME with compute-only contexts

Compute rings don't have PFP.

Fixes: a1378639ab1 "radeonsi: always use compute rings for clover on CI and newer (v2)"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
5 years agovirgl: define MAX_VERTEX_STREAMS based on availability of TF3
Gert Wollny [Wed, 13 Mar 2019 17:50:52 +0000 (18:50 +0100)]
virgl: define MAX_VERTEX_STREAMS based on availability of TF3

Since with gles hosts we lie about the GLSL feature level it is better
to set the number of streams based on actual hosts capabilities.

v2: Make use of feature check level to avoid regressions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agosoftpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADD
Gert Wollny [Tue, 19 Mar 2019 16:24:26 +0000 (17:24 +0100)]
softpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADD

This enables the following piglits with PASS:
  nv_shader_atomic_float/execution/
    shared-atomicadd-float
    shared-atomicexchange-float
    ssbo-atomicadd-float
    ssbo-atomicexchange-float

v2: Minimize the patch by using type punning (Eric Anholt)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agovirgl: stricter usage of compressed 3d textures
Erik Faye-Lund [Thu, 28 Mar 2019 18:03:47 +0000 (19:03 +0100)]
virgl: stricter usage of compressed 3d textures

Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of
OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc,
EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture,
S3_s3tc or EXT_texture_compression_s3tc specifications.

So let's not allow any of those compressed 3d-textures at all. It's not
going to work once it hits the OpenGL driver in virglrenderer.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agovirgl: do not allow compressed formats for buffers
Erik Faye-Lund [Fri, 29 Mar 2019 09:48:33 +0000 (10:48 +0100)]
virgl: do not allow compressed formats for buffers

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agodri3: Return the current swap interval from glXGetSwapIntervalMESA().
Eric Anholt [Fri, 29 Mar 2019 17:16:05 +0000 (10:16 -0700)]
dri3: Return the current swap interval from glXGetSwapIntervalMESA().

We were caching only the value set with glXSwapIntervalSGI(), missing out
on the default setting of the swap interval by the loader.  This fixes
glxgears's warning about being vblank synchronized by default.

Fixes: 9777c4234b0e ("loader: drop the [gs]et_swap_interval callbacks")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agointel: Add support for Comet Lake
Anuj Phogat [Fri, 29 Mar 2019 20:13:01 +0000 (13:13 -0700)]
intel: Add support for Comet Lake

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoiris: Adapt to variable ppGTT size
Chris Wilson [Mon, 1 Apr 2019 10:39:46 +0000 (11:39 +0100)]
iris: Adapt to variable ppGTT size

Not all hardware is made equal and some does not have the full
complement of 48b of address space. Ask what the actual size of virtual
address space allocated for contexts, and bail if that is not enough to
satisfy our static partitioning needs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoradv: partially enable VK_KHR_shader_float16_int8
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:11 +0000 (16:18 +0200)]
radv: partially enable VK_KHR_shader_float16_int8

Only 8-bit integers for now, float16 requires a bit more work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:10 +0000 (16:18 +0200)]
ac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit support to ac_build_umsb()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:09 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_build_umsb()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit support to ac_find_lsb()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:08 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_find_lsb()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit support to ac_build_bit_count()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:07 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_build_bit_count()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac/nir: add support for nir_op_b2i8
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:06 +0000 (16:18 +0200)]
ac/nir: add support for nir_op_b2i8

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: implement ARB/KHR_parallel_shader_compile callbacks
Marek Olšák [Mon, 6 Aug 2018 11:11:33 +0000 (07:11 -0400)]
radeonsi: implement ARB/KHR_parallel_shader_compile callbacks

5 years agoutil/queue: add util_queue_adjust_num_threads
Marek Olšák [Tue, 7 Aug 2018 00:40:05 +0000 (20:40 -0400)]
util/queue: add util_queue_adjust_num_threads

for ARB_parallel_shader_compile

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agoutil/queue: hold a lock when reading num_threads in util_queue_finish
Marek Olšák [Tue, 7 Aug 2018 00:34:24 +0000 (20:34 -0400)]
util/queue: hold a lock when reading num_threads in util_queue_finish

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agoutil/queue: add ability to kill a subset of threads
Marek Olšák [Tue, 7 Aug 2018 00:32:31 +0000 (20:32 -0400)]
util/queue: add ability to kill a subset of threads

for ARB_parallel_shader_compile

5 years agoutil/queue: move thread creation into a separate function
Marek Olšák [Tue, 7 Aug 2018 00:15:43 +0000 (20:15 -0400)]
util/queue: move thread creation into a separate function

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>