soc.git
3 years agocomment out adding mmu and dcache to pspec in MMU FSM
Luke Kenneth Casson Leighton [Thu, 29 Apr 2021 22:00:52 +0000 (23:00 +0100)]
comment out adding mmu and dcache to pspec in MMU FSM

3 years agomove dcache into Loadstore1
Luke Kenneth Casson Leighton [Thu, 29 Apr 2021 21:58:31 +0000 (22:58 +0100)]
move dcache into Loadstore1

3 years agoadd option to disable bus forwarding on SPRs and FAST regs.
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 18:51:02 +0000 (19:51 +0100)]
add option to disable bus forwarding on SPRs and FAST regs.
not StateRegs: that actually critically depends on access to PC through
bus forwarding

3 years agoadd option to enable/disable bus forwarding mode on INT regfile
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 18:46:57 +0000 (19:46 +0100)]
add option to enable/disable bus forwarding mode on INT regfile

3 years agoreturn read data out from Loadstore1 only when valid
Luke Kenneth Casson Leighton [Tue, 27 Apr 2021 18:46:24 +0000 (19:46 +0100)]
return read data out from Loadstore1 only when valid

3 years agohook up MSR into MMU (TODO, use a lot less bits)
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 20:45:10 +0000 (21:45 +0100)]
hook up MSR into MMU (TODO, use a lot less bits)

3 years agosimple regression dcache test was faulty. wishbone pipeline related
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 20:23:39 +0000 (21:23 +0100)]
simple regression dcache test was faulty.  wishbone pipeline related

3 years agocomment read ack in sram
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 09:32:42 +0000 (10:32 +0100)]
comment read ack in sram

3 years agoincorrect indentation in dcache rams
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 09:19:26 +0000 (10:19 +0100)]
incorrect indentation in dcache rams

3 years agosimplify dcache test
Luke Kenneth Casson Leighton [Mon, 26 Apr 2021 08:22:14 +0000 (09:22 +0100)]
simplify dcache test

3 years agospelling mistake
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 22:51:07 +0000 (23:51 +0100)]
spelling mistake

3 years agoremove RegStage1.real_adr temporary from dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 22:17:09 +0000 (23:17 +0100)]
remove RegStage1.real_adr temporary from dcache

3 years agodo not overwrite parameter ra in dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 22:03:05 +0000 (23:03 +0100)]
do not overwrite parameter ra in dcache

3 years agocomment out dcache_store from test, not the problem
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 21:22:49 +0000 (22:22 +0100)]
comment out dcache_store from test, not the problem

3 years agoremove unneeded code
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 21:02:01 +0000 (22:02 +0100)]
remove unneeded code

3 years agoread req in wb_in.stall, dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 20:35:22 +0000 (21:35 +0100)]
read req in wb_in.stall, dcache

3 years agoShift-out skipped mask bits for both crpred and intpred
Cesar Strauss [Sun, 25 Apr 2021 19:11:19 +0000 (16:11 -0300)]
Shift-out skipped mask bits for both crpred and intpred

If src/dest step are not zero, we need to shift-out the skipped mask
bits. We already did this for intpred, and for crpred it's exactly the
same.
Move the shifting logic to a new last state, commonly used for both
intpred and crpred.

3 years agoadd single regression test for dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 20:15:56 +0000 (21:15 +0100)]
add single regression test for dcache

3 years agoadd TODO comment in dcache
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 10:55:31 +0000 (11:55 +0100)]
add TODO comment in dcache

3 years agomove Signals in dcache to relevant context
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 10:46:50 +0000 (11:46 +0100)]
move Signals in dcache to relevant context

3 years agodcache Elif used where If should have been
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 10:43:35 +0000 (11:43 +0100)]
dcache Elif used where If should have been

3 years agowhoops should be cyc & ~ack
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 08:52:22 +0000 (09:52 +0100)]
whoops should be cyc & ~ack

3 years agohard-code dcache stall signal to non-pipelined mode
Luke Kenneth Casson Leighton [Sun, 25 Apr 2021 08:39:56 +0000 (09:39 +0100)]
hard-code dcache stall signal to non-pipelined mode

3 years agoincrease memory size in dcache test
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:26:32 +0000 (21:26 +0100)]
increase memory size in dcache test

3 years agoincrease size of random dcache testing by 10
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:18:18 +0000 (21:18 +0100)]
increase size of random dcache testing by 10

3 years agofix errors in dcache unit test
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:10:39 +0000 (21:10 +0100)]
fix errors in dcache unit test

3 years agowhitespace
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 20:10:27 +0000 (21:10 +0100)]
whitespace

3 years agoadd additional external libre-soc sphinx references... commented out for now
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 15:36:49 +0000 (16:36 +0100)]
add additional external libre-soc sphinx references... commented out for now

3 years agoadd additional external libre-soc sphinx references
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 15:36:26 +0000 (16:36 +0100)]
add additional external libre-soc sphinx references

3 years agoremove code moved to openpower-isa repo
Luke Kenneth Casson Leighton [Sat, 24 Apr 2021 10:51:24 +0000 (11:51 +0100)]
remove code moved to openpower-isa repo

3 years agoadd comments on TestIssuer TestRunner
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 22:17:11 +0000 (23:17 +0100)]
add comments on TestIssuer TestRunner

3 years agocomment tests back in
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 22:08:33 +0000 (23:08 +0100)]
comment tests back in

3 years agofix import error
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 22:08:03 +0000 (23:08 +0100)]
fix import error

3 years agoerror in setting fast regs test values
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 22:05:58 +0000 (23:05 +0100)]
error in setting fast regs test values

3 years agoimport from openpower.tests
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 21:59:39 +0000 (22:59 +0100)]
import from openpower.tests

3 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:31:16 +0000 (20:31 +0100)]
whitespace

3 years agomove logical tests to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:28:39 +0000 (20:28 +0100)]
move logical tests to openpower.test

3 years agoadd trap test cases
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:24:21 +0000 (20:24 +0100)]
add trap test cases
https://bugs.libre-soc.org/show_bug.cgi?id=629

3 years agomove SPR tests to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 19:06:20 +0000 (20:06 +0100)]
move SPR tests to openpower.test

3 years agomove branch test cases to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:54:15 +0000 (19:54 +0100)]
move branch test cases to openpower.test

3 years agomove LDST tests to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:49:07 +0000 (19:49 +0100)]
move LDST tests to openpower.test

3 years agomove mul tests to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:45:14 +0000 (19:45 +0100)]
move mul tests to openpower.test

3 years agomove div tests to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:38:35 +0000 (19:38 +0100)]
move div tests to openpower.test

3 years agomove div tests to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:37:33 +0000 (19:37 +0100)]
move div tests to openpower.test

3 years agomove ALU test cases to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:29:58 +0000 (19:29 +0100)]
move ALU test cases to openpower.test

3 years agomove MMU Testcase to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:23:47 +0000 (19:23 +0100)]
move MMU Testcase to openpower.test

3 years agomove CR test cases to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:14:00 +0000 (19:14 +0100)]
move CR test cases to openpower.test

3 years agomove shiftrot test cases to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 17:59:45 +0000 (18:59 +0100)]
move shiftrot test cases to openpower.test

3 years agoimport from openpower.endian
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 17:42:37 +0000 (18:42 +0100)]
import from openpower.endian

3 years agouse openpower.test.common
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 17:40:07 +0000 (18:40 +0100)]
use openpower.test.common

3 years agoremove openpower-isa submodule
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 16:49:15 +0000 (17:49 +0100)]
remove openpower-isa submodule

3 years agosubmodule update, can probably delete it though, now
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 16:48:09 +0000 (17:48 +0100)]
submodule update, can probably delete it though, now

3 years agomove more files to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 16:10:05 +0000 (17:10 +0100)]
move more files to openpower-isa

3 years agomove to import from openpower-isa for reg enums
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:55:53 +0000 (16:55 +0100)]
move to import from openpower-isa for reg enums

3 years agosvanalysis and pywriter now command-line scripts
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:47:05 +0000 (16:47 +0100)]
svanalysis and pywriter now command-line scripts

3 years agoremoved submodule
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:33:56 +0000 (16:33 +0100)]
removed submodule

3 years agoremove pseudo, moved to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:32:58 +0000 (16:32 +0100)]
remove pseudo, moved to openpower-isa

3 years agoremove simulator directory, moved to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:16:00 +0000 (16:16 +0100)]
remove simulator directory, moved to openpower-isa

3 years agomore openpower-isa conversion
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:14:01 +0000 (16:14 +0100)]
more openpower-isa conversion

3 years agocorrect migration of openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:44:56 +0000 (15:44 +0100)]
correct migration of openpower-isa

3 years agomore openpower import conversion
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:42:29 +0000 (15:42 +0100)]
more openpower import conversion

3 years agomore openpower import conversion
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:38:16 +0000 (15:38 +0100)]
more openpower import conversion

3 years agomove over to from openpower imports
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:30:39 +0000 (15:30 +0100)]
move over to from openpower imports

3 years agomove over to openpower-isa repo
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:26:03 +0000 (15:26 +0100)]
move over to openpower-isa repo

3 years agomove over to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:21:15 +0000 (15:21 +0100)]
move over to openpower-isa

3 years agomoving more over to openpower-isa repo
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:19:43 +0000 (15:19 +0100)]
moving more over to openpower-isa repo

3 years agoremoving more as moved over to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:16:23 +0000 (15:16 +0100)]
removing more as moved over to openpower-isa

3 years agosubmodule update
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 12:14:07 +0000 (13:14 +0100)]
submodule update

3 years agoadd debugging and buffering to CacheRam
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 22:59:56 +0000 (23:59 +0100)]
add debugging and buffering to CacheRam

3 years agowhitespace
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:38:50 +0000 (16:38 +0100)]
whitespace

3 years agor1.end_row_ix off-by-one in dcache
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:31:23 +0000 (16:31 +0100)]
r1.end_row_ix off-by-one in dcache

3 years agosync missing in dcache
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:22:41 +0000 (16:22 +0100)]
sync missing in dcache

3 years agodcache.py code-comments
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:21:14 +0000 (16:21 +0100)]
dcache.py code-comments

3 years agocleanup dcache
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 14:16:12 +0000 (15:16 +0100)]
cleanup dcache

3 years agoerror using sync, should have been comb
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 14:05:37 +0000 (15:05 +0100)]
error using sync, should have been comb

3 years agoImplement CR predication
Cesar Strauss [Wed, 21 Apr 2021 20:30:12 +0000 (17:30 -0300)]
Implement CR predication

Read the CR fields in a VL loop, building the masks bit by bit.
TODO: implement reentrancy, by shifting out already used mask bits.

3 years agoCR sub-fields are stored in MSB0 order
Cesar Strauss [Wed, 21 Apr 2021 19:42:56 +0000 (16:42 -0300)]
CR sub-fields are stored in MSB0 order

3 years agoexperimenting with dcache
Luke Kenneth Casson Leighton [Wed, 21 Apr 2021 19:50:54 +0000 (20:50 +0100)]
experimenting with dcache

3 years agotestcase: pass PRTBL to mmu
Tobias Platen [Wed, 21 Apr 2021 18:48:38 +0000 (20:48 +0200)]
testcase: pass PRTBL to mmu

3 years agoAdd CR predication test case for TestIssuer
Cesar Strauss [Wed, 21 Apr 2021 17:43:57 +0000 (14:43 -0300)]
Add CR predication test case for TestIssuer

Directly derived from the corresponding case in
test_caller_svp64_predication.py
It is expected to fail, until CR predication is implemented on TestIssuer.

3 years agoFix comment in CR predication test case
Cesar Strauss [Wed, 21 Apr 2021 17:22:55 +0000 (14:22 -0300)]
Fix comment in CR predication test case

The comment at the top of the test case was inconsistent with it:
"adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)"
The whole test is consistent with this (mask is NE and first element is
skipped).
The shift amount itself is also consistent with setting of CR4, not CR5.

3 years agoFix sense of "invert" signal
Cesar Strauss [Wed, 21 Apr 2021 17:06:07 +0000 (14:06 -0300)]
Fix sense of "invert" signal

We want to put "1" in the mask, if the operation is to be performed.
The actual CR bits are: LT, GT, EQ and SO.
So, for those, we just copy the bit directly to the mask, as they are.
For GE, LE, NE and NS, we want to invert the bit first.

3 years agoadd enable MMU option to issuer_verilog.py
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 16:10:39 +0000 (17:10 +0100)]
add enable MMU option to issuer_verilog.py

3 years agocannot pass in arguments to Core - must be done with pspec
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 15:57:52 +0000 (16:57 +0100)]
cannot pass in arguments to Core - must be done with pspec

3 years agouse soc.bus.sram instead of nmigen_soc.wishbone.sram
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 14:37:24 +0000 (15:37 +0100)]
use soc.bus.sram instead of nmigen_soc.wishbone.sram

3 years agoadd wishbone sram.py (move from nmigen-soc)
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 14:34:34 +0000 (15:34 +0100)]
add wishbone sram.py (move from nmigen-soc)

3 years agogive independent names to spblock512w64b8ws
Luke Kenneth Casson Leighton [Mon, 19 Apr 2021 17:55:50 +0000 (18:55 +0100)]
give independent names to spblock512w64b8ws

3 years agogive spblock512 a name as a submodule
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 22:42:48 +0000 (23:42 +0100)]
give spblock512 a name as a submodule

3 years agocreate signal on test_issuer which gives PLL clk_sel_i a useful name
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:27:30 +0000 (21:27 +0100)]
create signal on test_issuer which gives PLL clk_sel_i a useful name

3 years agorename SPBlock_512W64B8W to lowercase
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:17:34 +0000 (21:17 +0100)]
rename SPBlock_512W64B8W to lowercase

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:06:40 +0000 (21:06 +0100)]
submodule update

3 years agorename PLL pins to match LIP6.fr PLL
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:06:10 +0000 (21:06 +0100)]
rename PLL pins to match LIP6.fr PLL

3 years agocore_stopped_i unused: remove
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 19:01:43 +0000 (20:01 +0100)]
core_stopped_i unused: remove

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 18:26:26 +0000 (19:26 +0100)]
submodule update

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 15:42:57 +0000 (16:42 +0100)]
submodule update

3 years agoadd pypi upload to Makefile
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 12:21:19 +0000 (13:21 +0100)]
add pypi upload to Makefile

3 years agoadd OS Independent classifier
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 11:44:36 +0000 (12:44 +0100)]
add OS Independent classifier

3 years agoupdate README
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:18:59 +0000 (11:18 +0100)]
update README

3 years agoupdate setup.py to make it "safe" for uploading to pypi
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:09:43 +0000 (11:09 +0100)]
update setup.py to make it "safe" for uploading to pypi

3 years agoexperiment with alternative PID in radix mmu
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:27:39 +0000 (20:27 +0100)]
experiment with alternative PID in radix mmu