soc.git
3 years agomove div tests to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:37:33 +0000 (19:37 +0100)]
move div tests to openpower.test

3 years agomove ALU test cases to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:29:58 +0000 (19:29 +0100)]
move ALU test cases to openpower.test

3 years agomove MMU Testcase to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:23:47 +0000 (19:23 +0100)]
move MMU Testcase to openpower.test

3 years agomove CR test cases to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 18:14:00 +0000 (19:14 +0100)]
move CR test cases to openpower.test

3 years agomove shiftrot test cases to openpower.test
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 17:59:45 +0000 (18:59 +0100)]
move shiftrot test cases to openpower.test

3 years agoimport from openpower.endian
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 17:42:37 +0000 (18:42 +0100)]
import from openpower.endian

3 years agouse openpower.test.common
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 17:40:07 +0000 (18:40 +0100)]
use openpower.test.common

3 years agoremove openpower-isa submodule
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 16:49:15 +0000 (17:49 +0100)]
remove openpower-isa submodule

3 years agosubmodule update, can probably delete it though, now
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 16:48:09 +0000 (17:48 +0100)]
submodule update, can probably delete it though, now

3 years agomove more files to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 16:10:05 +0000 (17:10 +0100)]
move more files to openpower-isa

3 years agomove to import from openpower-isa for reg enums
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:55:53 +0000 (16:55 +0100)]
move to import from openpower-isa for reg enums

3 years agosvanalysis and pywriter now command-line scripts
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:47:05 +0000 (16:47 +0100)]
svanalysis and pywriter now command-line scripts

3 years agoremoved submodule
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:33:56 +0000 (16:33 +0100)]
removed submodule

3 years agoremove pseudo, moved to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:32:58 +0000 (16:32 +0100)]
remove pseudo, moved to openpower-isa

3 years agoremove simulator directory, moved to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:16:00 +0000 (16:16 +0100)]
remove simulator directory, moved to openpower-isa

3 years agomore openpower-isa conversion
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 15:14:01 +0000 (16:14 +0100)]
more openpower-isa conversion

3 years agocorrect migration of openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:44:56 +0000 (15:44 +0100)]
correct migration of openpower-isa

3 years agomore openpower import conversion
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:42:29 +0000 (15:42 +0100)]
more openpower import conversion

3 years agomore openpower import conversion
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:38:16 +0000 (15:38 +0100)]
more openpower import conversion

3 years agomove over to from openpower imports
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:30:39 +0000 (15:30 +0100)]
move over to from openpower imports

3 years agomove over to openpower-isa repo
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:26:03 +0000 (15:26 +0100)]
move over to openpower-isa repo

3 years agomove over to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:21:15 +0000 (15:21 +0100)]
move over to openpower-isa

3 years agomoving more over to openpower-isa repo
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:19:43 +0000 (15:19 +0100)]
moving more over to openpower-isa repo

3 years agoremoving more as moved over to openpower-isa
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 14:16:23 +0000 (15:16 +0100)]
removing more as moved over to openpower-isa

3 years agosubmodule update
Luke Kenneth Casson Leighton [Fri, 23 Apr 2021 12:14:07 +0000 (13:14 +0100)]
submodule update

3 years agoadd debugging and buffering to CacheRam
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 22:59:56 +0000 (23:59 +0100)]
add debugging and buffering to CacheRam

3 years agowhitespace
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:38:50 +0000 (16:38 +0100)]
whitespace

3 years agor1.end_row_ix off-by-one in dcache
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:31:23 +0000 (16:31 +0100)]
r1.end_row_ix off-by-one in dcache

3 years agosync missing in dcache
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:22:41 +0000 (16:22 +0100)]
sync missing in dcache

3 years agodcache.py code-comments
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 15:21:14 +0000 (16:21 +0100)]
dcache.py code-comments

3 years agocleanup dcache
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 14:16:12 +0000 (15:16 +0100)]
cleanup dcache

3 years agoerror using sync, should have been comb
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 14:05:37 +0000 (15:05 +0100)]
error using sync, should have been comb

3 years agoImplement CR predication
Cesar Strauss [Wed, 21 Apr 2021 20:30:12 +0000 (17:30 -0300)]
Implement CR predication

Read the CR fields in a VL loop, building the masks bit by bit.
TODO: implement reentrancy, by shifting out already used mask bits.

3 years agoCR sub-fields are stored in MSB0 order
Cesar Strauss [Wed, 21 Apr 2021 19:42:56 +0000 (16:42 -0300)]
CR sub-fields are stored in MSB0 order

3 years agoexperimenting with dcache
Luke Kenneth Casson Leighton [Wed, 21 Apr 2021 19:50:54 +0000 (20:50 +0100)]
experimenting with dcache

3 years agotestcase: pass PRTBL to mmu
Tobias Platen [Wed, 21 Apr 2021 18:48:38 +0000 (20:48 +0200)]
testcase: pass PRTBL to mmu

3 years agoAdd CR predication test case for TestIssuer
Cesar Strauss [Wed, 21 Apr 2021 17:43:57 +0000 (14:43 -0300)]
Add CR predication test case for TestIssuer

Directly derived from the corresponding case in
test_caller_svp64_predication.py
It is expected to fail, until CR predication is implemented on TestIssuer.

3 years agoFix comment in CR predication test case
Cesar Strauss [Wed, 21 Apr 2021 17:22:55 +0000 (14:22 -0300)]
Fix comment in CR predication test case

The comment at the top of the test case was inconsistent with it:
"adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)"
The whole test is consistent with this (mask is NE and first element is
skipped).
The shift amount itself is also consistent with setting of CR4, not CR5.

3 years agoFix sense of "invert" signal
Cesar Strauss [Wed, 21 Apr 2021 17:06:07 +0000 (14:06 -0300)]
Fix sense of "invert" signal

We want to put "1" in the mask, if the operation is to be performed.
The actual CR bits are: LT, GT, EQ and SO.
So, for those, we just copy the bit directly to the mask, as they are.
For GE, LE, NE and NS, we want to invert the bit first.

3 years agoadd enable MMU option to issuer_verilog.py
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 16:10:39 +0000 (17:10 +0100)]
add enable MMU option to issuer_verilog.py

3 years agocannot pass in arguments to Core - must be done with pspec
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 15:57:52 +0000 (16:57 +0100)]
cannot pass in arguments to Core - must be done with pspec

3 years agouse soc.bus.sram instead of nmigen_soc.wishbone.sram
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 14:37:24 +0000 (15:37 +0100)]
use soc.bus.sram instead of nmigen_soc.wishbone.sram

3 years agoadd wishbone sram.py (move from nmigen-soc)
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 14:34:34 +0000 (15:34 +0100)]
add wishbone sram.py (move from nmigen-soc)

3 years agogive independent names to spblock512w64b8ws
Luke Kenneth Casson Leighton [Mon, 19 Apr 2021 17:55:50 +0000 (18:55 +0100)]
give independent names to spblock512w64b8ws

3 years agogive spblock512 a name as a submodule
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 22:42:48 +0000 (23:42 +0100)]
give spblock512 a name as a submodule

3 years agocreate signal on test_issuer which gives PLL clk_sel_i a useful name
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:27:30 +0000 (21:27 +0100)]
create signal on test_issuer which gives PLL clk_sel_i a useful name

3 years agorename SPBlock_512W64B8W to lowercase
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:17:34 +0000 (21:17 +0100)]
rename SPBlock_512W64B8W to lowercase

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:06:40 +0000 (21:06 +0100)]
submodule update

3 years agorename PLL pins to match LIP6.fr PLL
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:06:10 +0000 (21:06 +0100)]
rename PLL pins to match LIP6.fr PLL

3 years agocore_stopped_i unused: remove
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 19:01:43 +0000 (20:01 +0100)]
core_stopped_i unused: remove

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 18:26:26 +0000 (19:26 +0100)]
submodule update

3 years agosubmodule update
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 15:42:57 +0000 (16:42 +0100)]
submodule update

3 years agoadd pypi upload to Makefile
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 12:21:19 +0000 (13:21 +0100)]
add pypi upload to Makefile

3 years agoadd OS Independent classifier
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 11:44:36 +0000 (12:44 +0100)]
add OS Independent classifier

3 years agoupdate README
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:18:59 +0000 (11:18 +0100)]
update README

3 years agoupdate setup.py to make it "safe" for uploading to pypi
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 10:09:43 +0000 (11:09 +0100)]
update setup.py to make it "safe" for uploading to pypi

3 years agoexperiment with alternative PID in radix mmu
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:27:39 +0000 (20:27 +0100)]
experiment with alternative PID in radix mmu

3 years agopass in SPRs each time on radix test
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:16:59 +0000 (20:16 +0100)]
pass in SPRs each time on radix test
allows for different tests

3 years agoadd LD/ST radix unit test
Luke Kenneth Casson Leighton [Sat, 17 Apr 2021 19:03:34 +0000 (20:03 +0100)]
add LD/ST radix unit test

3 years agoImplement 1<<r3 directly by a shift
Cesar Strauss [Sat, 17 Apr 2021 18:12:29 +0000 (15:12 -0300)]
Implement 1<<r3 directly by a shift

It generates simpler Yosys graphs.

3 years agoradixmmu: fix my mistake about pgbase size
Tobias Platen [Sat, 17 Apr 2021 17:22:12 +0000 (19:22 +0200)]
radixmmu: fix my mistake about pgbase size

3 years agosubmodule update
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 22:46:02 +0000 (23:46 +0100)]
submodule update

3 years agojtag utils, send tms before tck
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 19:49:29 +0000 (20:49 +0100)]
jtag utils, send tms before tck

3 years agopass the "old" value of shift to _new_lookup
Tobias Platen [Fri, 16 Apr 2021 19:26:19 +0000 (21:26 +0200)]
pass the "old" value of shift to _new_lookup

3 years agosigh, new_shift wrong bitwidth
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 18:03:58 +0000 (19:03 +0100)]
sigh, new_shift wrong bitwidth

3 years agoput mbits back into segment_check (like it is in microwatt)
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:28:29 +0000 (01:28 +0100)]
put mbits back into segment_check (like it is in microwatt)

3 years agoradixmmu cleanup
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:08:51 +0000 (01:08 +0100)]
radixmmu cleanup

3 years agocall addrshift and get_pgtable_addr inside while loop for radixmmu
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:04:07 +0000 (01:04 +0100)]
call addrshift and get_pgtable_addr inside while loop for radixmmu

3 years agocode-cleanup in radixmmu
Luke Kenneth Casson Leighton [Fri, 16 Apr 2021 00:00:01 +0000 (01:00 +0100)]
code-cleanup in radixmmu

3 years agowhitespace and corrections to NLS, RTS1, RTS2
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 23:21:09 +0000 (00:21 +0100)]
whitespace and corrections to NLS, RTS1, RTS2

3 years agofix radix testcase
Tobias Platen [Thu, 15 Apr 2021 17:05:51 +0000 (19:05 +0200)]
fix radix testcase

3 years agoconcat en_sigs together in JTAG to make sure they are not missed out
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 15:43:12 +0000 (16:43 +0100)]
concat en_sigs together in JTAG to make sure they are not missed out

3 years agoadd icachemmu option to ISACaller
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 08:48:37 +0000 (09:48 +0100)]
add icachemmu option to ISACaller

3 years agosubmodule update
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:38 +0000 (20:08 +0100)]
submodule update

3 years agowhitespace
Luke Kenneth Casson Leighton [Wed, 14 Apr 2021 19:08:28 +0000 (20:08 +0100)]
whitespace

3 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 13 Apr 2021 16:04:24 +0000 (17:04 +0100)]
submodule update

3 years agoupdate test_caller_radix.py
Tobias Platen [Wed, 14 Apr 2021 18:22:20 +0000 (20:22 +0200)]
update test_caller_radix.py

3 years agoradixmmu: handle badtree
Tobias Platen [Wed, 14 Apr 2021 18:16:00 +0000 (20:16 +0200)]
radixmmu: handle badtree

3 years agoupdate test case for radix mmu
Tobias Platen [Wed, 14 Apr 2021 17:39:08 +0000 (19:39 +0200)]
update test case for radix mmu

3 years agoradixmmu: error handling
Tobias Platen [Wed, 14 Apr 2021 17:34:13 +0000 (19:34 +0200)]
radixmmu: error handling

3 years agomore fixes for radixmmu.py
Tobias Platen [Tue, 13 Apr 2021 17:21:18 +0000 (19:21 +0200)]
more fixes for radixmmu.py

3 years agofix AttributeError in radixmmu testcase
Tobias Platen [Tue, 13 Apr 2021 16:43:37 +0000 (18:43 +0200)]
fix AttributeError in radixmmu testcase

3 years agoradixmmu.py: cleanup
Tobias Platen [Mon, 12 Apr 2021 17:50:20 +0000 (19:50 +0200)]
radixmmu.py: cleanup

3 years agofix bug in radixmmu.py
Tobias Platen [Sun, 11 Apr 2021 18:48:12 +0000 (20:48 +0200)]
fix bug in radixmmu.py

3 years agoradixmmu: more work on segment check
Tobias Platen [Sun, 11 Apr 2021 06:45:06 +0000 (08:45 +0200)]
radixmmu: more work on segment check

3 years agoImplement 1<<r3 predicate mode
Cesar Strauss [Sat, 10 Apr 2021 20:27:48 +0000 (17:27 -0300)]
Implement 1<<r3 predicate mode

The mask bit selected by r3 is set to one.
A possible optimization would be to do step = r3 directly, but this is only
valid in non-zero mode.
The corresponding test cases now pass.

3 years agoAdd 1<<r3 test cases to TestIssuer
Cesar Strauss [Sat, 10 Apr 2021 19:59:19 +0000 (16:59 -0300)]
Add 1<<r3 test cases to TestIssuer

They fail, since it's not implemented yet.

3 years agoAdd test cases for 1<<r3 predication
Cesar Strauss [Sat, 10 Apr 2021 19:40:09 +0000 (16:40 -0300)]
Add test cases for 1<<r3 predication

3 years agoadd blinken lights assembly (not used yet)
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 11:40:48 +0000 (12:40 +0100)]
add blinken lights assembly (not used yet)

3 years agotest firmware upload program needed to branch back further in order to loop
Luke Kenneth Casson Leighton [Fri, 9 Apr 2021 00:09:32 +0000 (01:09 +0100)]
test firmware upload program needed to branch back further in order to loop

3 years agosort out pc reset when DMI interface requests reset
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 23:24:42 +0000 (00:24 +0100)]
sort out pc reset when DMI interface requests reset

3 years agosubmodule update
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:31 +0000 (21:53 +0100)]
submodule update

3 years agoargh, wb jtag stall probably is not working
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:53:03 +0000 (21:53 +0100)]
argh, wb jtag stall probably is not working

3 years agoupload over 32-bit JTAG Wishbone
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:38:55 +0000 (21:38 +0100)]
upload over 32-bit JTAG Wishbone

3 years agoshrink JTAG master bus to 32-bit (match with litex)
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:21:09 +0000 (21:21 +0100)]
shrink JTAG master bus to 32-bit (match with litex)

3 years agosubmodule update
Luke Kenneth Casson Leighton [Wed, 7 Apr 2021 19:27:37 +0000 (20:27 +0100)]
submodule update

3 years agoWIP: calculate address of first page table entry
Tobias Platen [Wed, 7 Apr 2021 19:17:35 +0000 (21:17 +0200)]
WIP: calculate address of first page table entry

3 years agoradixmmu: fix segment_check function and its caller
Tobias Platen [Wed, 7 Apr 2021 18:26:54 +0000 (20:26 +0200)]
radixmmu: fix segment_check function and its caller

3 years ago4k SRAM Instance needs write-enable @ 8-bit width
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 21:07:12 +0000 (22:07 +0100)]
4k SRAM Instance needs write-enable @ 8-bit width

3 years ago8-bit granularity on JTAG wishbone
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:38:04 +0000 (21:38 +0100)]
8-bit granularity on JTAG wishbone