Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 12:51:21 +0000 (12:51 +0000)]
add in SVSTATE to ISACaller, not used, just passed in
Luke Kenneth Casson Leighton [Thu, 11 Feb 2021 15:57:25 +0000 (15:57 +0000)]
comments in TestIssuer for SVP64PrefixDecoder
Luke Kenneth Casson Leighton [Wed, 10 Feb 2021 15:25:06 +0000 (15:25 +0000)]
add svp64 reg decode detection to ISACaller output
Luke Kenneth Casson Leighton [Tue, 9 Feb 2021 19:46:02 +0000 (19:46 +0000)]
starting to add SVP64 register EXTRA-read and isvec to ISACaller
Luke Kenneth Casson Leighton [Thu, 4 Feb 2021 16:53:53 +0000 (16:53 +0000)]
comment update
colepoirier [Tue, 9 Feb 2021 22:38:47 +0000 (14:38 -0800)]
add missing newline at end of experiment/formal/.gitignore
colepoirier [Tue, 9 Feb 2021 22:36:31 +0000 (14:36 -0800)]
fix erroneous removal of proof* from experiment/formal/.gitignore, now
proof*/**
colepoirier [Sun, 7 Feb 2021 22:33:43 +0000 (14:33 -0800)]
add skeleton implementation of experiment/formal/proof_icache.py to
so I can solicit help
colepoirier [Sun, 7 Feb 2021 22:33:14 +0000 (14:33 -0800)]
icache.py fix formatting
colepoirier [Sun, 7 Feb 2021 22:30:16 +0000 (14:30 -0800)]
Modify experiment/formal/.gitignore because was preventing commiting
proof_icache.py
Cesar Strauss [Sat, 6 Feb 2021 21:33:26 +0000 (18:33 -0300)]
Fix whitespace
Cesar Strauss [Sat, 6 Feb 2021 20:53:22 +0000 (17:53 -0300)]
Extract the fetch FSM out from the main FSM
Allows future extension to prefixed instructions, as well as being an
opportunity for pipeline optimization.
At start, the fetch FSM waits for the PC to be stable. This
happens when there is no longer an instruction being executed.
When done, it hands over the instruction to the decoder.
Tobias Platen [Fri, 5 Feb 2021 20:01:08 +0000 (21:01 +0100)]
fix hanging simulation
Tobias Platen [Thu, 4 Feb 2021 20:01:38 +0000 (21:01 +0100)]
src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
Tobias Platen [Thu, 4 Feb 2021 19:26:51 +0000 (20:26 +0100)]
update test_issuer_mmu_data_path.py to handle SPRs
Tobias Platen [Thu, 4 Feb 2021 19:19:39 +0000 (20:19 +0100)]
pass SPR MicroOp to MMU function unit
Luke Kenneth Casson Leighton [Wed, 3 Feb 2021 21:26:15 +0000 (21:26 +0000)]
nope - need it to be zero if not identified as svp64
Luke Kenneth Casson Leighton [Wed, 3 Feb 2021 21:24:05 +0000 (21:24 +0000)]
actually no need to mux in the svp64_rm, just the id "is this svp64" is enough
Luke Kenneth Casson Leighton [Wed, 3 Feb 2021 21:23:22 +0000 (21:23 +0000)]
add SVP64PowerDecoder, extracts svp64 remap if correctly identified
Luke Kenneth Casson Leighton [Mon, 1 Feb 2021 21:23:22 +0000 (21:23 +0000)]
ISACaller, in svp64 mode, read the next 32 bits when SVP64 identified
Tobias Platen [Mon, 1 Feb 2021 20:07:53 +0000 (21:07 +0100)]
extending the GTKWave document in test_issuer when microwatt_mmu = True
Luke Kenneth Casson Leighton [Mon, 1 Feb 2021 14:49:01 +0000 (14:49 +0000)]
sort out SelectableInt bit-ordering for identifying SVP64 fields
Luke Kenneth Casson Leighton [Mon, 1 Feb 2021 14:21:49 +0000 (14:21 +0000)]
construct the assembly-code prefix and base v3.0B in SVP64Asm class
Cesar Strauss [Mon, 1 Feb 2021 09:43:36 +0000 (06:43 -0300)]
Add GTKWave document to test_issuer
Cesar Strauss [Sun, 31 Jan 2021 20:18:18 +0000 (17:18 -0300)]
Fix loop test and enable it
Make the code correspond to the comments and vice-versa.
Due to the branching, this test is useful for ensuring correctness of the
interaction between instruction fetch and issue.
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 20:42:29 +0000 (20:42 +0000)]
start an ISACaller SVP64 unit test
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 20:28:27 +0000 (20:28 +0000)]
test SVP64 major opcode, start checking if it is EXT001 soon
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 20:04:10 +0000 (20:04 +0000)]
adjusting ISACaller unit test to use ISACaller.setup_one()
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 19:51:27 +0000 (19:51 +0000)]
fix ISACaller unit test
Tobias Platen [Sun, 31 Jan 2021 18:48:18 +0000 (19:48 +0100)]
fix two syntax errors in src/soc/decoder/isa/caller.py
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 18:03:01 +0000 (18:03 +0000)]
SVP64 Remap Fields structures for ISACaller
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 16:01:16 +0000 (16:01 +0000)]
remove sv_rm from PowerDecoder register decoders
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 15:53:19 +0000 (15:53 +0000)]
add SVSTATE SPR sub-field accessor class to ISACaller
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 15:28:02 +0000 (15:28 +0000)]
move SVP64 Extra reg decoding into main PowerDecoder module
Luke Kenneth Casson Leighton [Sun, 31 Jan 2021 15:08:29 +0000 (15:08 +0000)]
update submodule
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 17:53:21 +0000 (17:53 +0000)]
move CR in/out SVP64 EXTRA decoders into PowerDecoder
this due to satellite SubsetPowerDecoders containing unnecessary SVP64decoders
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 14:04:02 +0000 (14:04 +0000)]
add SVP64 CR out extending to 7-bit in PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 13:55:55 +0000 (13:55 +0000)]
add SVP64 CR EXTRA field-extension, from 3-bit to 7-bit (plus isvec)
in PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 13:17:45 +0000 (13:17 +0000)]
extend CR registers in Decode2ToExecute1Type to 7 bit
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 13:10:16 +0000 (13:10 +0000)]
add SVP64CRExtra class to PowerDecoder2, turns 3-bit CR into 7-bit plus isvec
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 12:55:21 +0000 (12:55 +0000)]
split out SVEXTRA field selection/decoding into separate class SVP64ExtraSpec
in PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 12:46:38 +0000 (12:46 +0000)]
whoops update PowerDecoder2 svp64 comments, reg sizes (7 bit)
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 00:36:22 +0000 (00:36 +0000)]
add SVP64 EXTRA decoding to RB, RC and RT (out) in PowerDecode2
DecodeOut2 will have to wait because it is more complex
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 00:17:20 +0000 (00:17 +0000)]
add first SVP64 7-bit register context decoder to PowerDecoder2
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 23:01:06 +0000 (23:01 +0000)]
add SVP64RM record to PowerDecoder2
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 23:00:46 +0000 (23:00 +0000)]
increase register number sizes from 5 to 7
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:51:37 +0000 (22:51 +0000)]
syntax corrections, also size of maxvl was wrong
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:46:43 +0000 (22:46 +0000)]
add SVP64 RM (Remap) Record
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:39:44 +0000 (22:39 +0000)]
adjust SVP64RM class to output more PowerDecoder-friendly csv augmentation
add SVEXTRA power_enum
extend PowerDecoder fields (sv in/out regs)
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 18:42:08 +0000 (18:42 +0000)]
adjust how register copy/setup is done in PowerDecoder2
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 14:59:49 +0000 (14:59 +0000)]
add SV etype/ptype to power decoder
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 12:12:12 +0000 (12:12 +0000)]
whoops syntax error. submodule update
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:56:35 +0000 (11:56 +0000)]
start adding svp64 enums
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:33:22 +0000 (11:33 +0000)]
use new svp64-augmented csv reader in PowerDecoder
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:19:14 +0000 (11:19 +0000)]
whoops missed out "+" on explicit license listing
Luke Kenneth Casson Leighton [Thu, 28 Jan 2021 16:07:29 +0000 (16:07 +0000)]
add SVSTATE to StateRegs
(also fix comments)
Luke Kenneth Casson Leighton [Thu, 28 Jan 2021 15:53:50 +0000 (15:53 +0000)]
add SVState SPR Record, SVSTATERec
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 18:38:34 +0000 (18:38 +0000)]
add svp64 CR field identification for EXTRA2/3 decoding
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 18:16:47 +0000 (18:16 +0000)]
move svp64 reg-decode function to more appropriate location
use it in SVP64RM get_svp64_csv to decode EXTRA bit-field positions
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:49:05 +0000 (12:49 +0000)]
provide "merger" of SVP64 RM info into v3.0B CSV files
Tobias Platen [Wed, 27 Jan 2021 19:45:37 +0000 (20:45 +0100)]
use SPR constants
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:38:35 +0000 (12:38 +0000)]
move SVP64RM CSV class to new module
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:35:30 +0000 (12:35 +0000)]
whitespace and shortening of SPR MMU redirection in Power Decoder
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:25:40 +0000 (12:25 +0000)]
also read LDST RM files
Tobias Platen [Tue, 26 Jan 2021 19:37:41 +0000 (20:37 +0100)]
[Bug 580] update comment above changed block
Tobias Platen [Tue, 26 Jan 2021 19:27:40 +0000 (20:27 +0100)]
[Bug 580] redirect MMU SPRs to the MMU
Luke Kenneth Casson Leighton [Mon, 25 Jan 2021 16:23:07 +0000 (16:23 +0000)]
extra comments in svp64
Luke Kenneth Casson Leighton [Sun, 24 Jan 2021 11:35:43 +0000 (11:35 +0000)]
changing svp64 asm syntax to use / instead of . as separators
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 21:43:36 +0000 (21:43 +0000)]
move sanity-checks, add mode into svp64_rm
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 21:39:26 +0000 (21:39 +0000)]
cleanup on aisle 3 - simplify sv_mode svp64
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 21:30:30 +0000 (21:30 +0000)]
check src/dest mask exist if zeroing, svp64
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 20:58:03 +0000 (20:58 +0000)]
add predicate-result svp64 decoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 20:50:30 +0000 (20:50 +0000)]
add svp64 saturation decoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 20:44:58 +0000 (20:44 +0000)]
start decoding modes in svp64
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 19:19:47 +0000 (19:19 +0000)]
and now for something completely different...
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 19:14:19 +0000 (19:14 +0000)]
add elwidth encoding svp64, add more debug-print
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 18:41:28 +0000 (18:41 +0000)]
add svp64 subvl encoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 18:35:33 +0000 (18:35 +0000)]
add in svp64 predicate mask encoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 18:03:41 +0000 (18:03 +0000)]
capture CR 3 and 5 bit sv encodings
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 16:01:02 +0000 (16:01 +0000)]
start decoding EXTRA2/3
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 15:38:17 +0000 (15:38 +0000)]
start decoding sv EXTRAs and identifying them
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 15:02:59 +0000 (15:02 +0000)]
start to read RM CSV files
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 13:23:58 +0000 (13:23 +0000)]
add beginnings of svp64 assembly translator
Luke Kenneth Casson Leighton [Fri, 22 Jan 2021 20:04:31 +0000 (20:04 +0000)]
add example on how to access regs list for cmp
Tobias Platen [Tue, 19 Jan 2021 18:54:45 +0000 (19:54 +0100)]
test_issuer_mmu_data_path.py: test both ld and st instructions
Tobias Platen [Tue, 19 Jan 2021 18:40:07 +0000 (19:40 +0100)]
connect LDSTException to MMU and DCache
Tobias Platen [Tue, 19 Jan 2021 17:21:50 +0000 (18:21 +0100)]
connect wishbone bus to test memory
Tobias Platen [Mon, 18 Jan 2021 19:51:59 +0000 (20:51 +0100)]
uncomment #FIXME in unit_test
Tobias Platen [Mon, 18 Jan 2021 17:25:13 +0000 (18:25 +0100)]
fu/mmu/fsm.py: connect valid and load signals
Tobias Platen [Sun, 17 Jan 2021 16:48:26 +0000 (17:48 +0100)]
add test memory for simulation
Tobias Platen [Sun, 17 Jan 2021 15:59:22 +0000 (16:59 +0100)]
cleanup test_issuer_mmu_data_path.py
Tobias Platen [Sat, 16 Jan 2021 17:31:48 +0000 (18:31 +0100)]
clean up test case for tlbie and dcbz
Tobias Platen [Sat, 16 Jan 2021 16:43:46 +0000 (17:43 +0100)]
move microwatt_mmu bool variable to pspec
Tobias Platen [Sat, 16 Jan 2021 10:00:07 +0000 (11:00 +0100)]
add new unittest: test_issuer_mmu_data_path.py
Tobias Platen [Fri, 15 Jan 2021 18:16:57 +0000 (19:16 +0100)]
cleanup test_non_production_core.py
Tobias Platen [Fri, 15 Jan 2021 18:05:36 +0000 (19:05 +0100)]
add microwatt_mmu boolean variable to core and compunits
Tobias Platen [Fri, 15 Jan 2021 17:56:18 +0000 (18:56 +0100)]
test_non_production_core.py: fix hanging test
Tobias Platen [Fri, 15 Jan 2021 16:50:16 +0000 (17:50 +0100)]
test_non_production_core.py: wire instruction decoder to core
Tobias Platen [Thu, 14 Jan 2021 20:06:55 +0000 (21:06 +0100)]
add test case for mmu+NonProductionCore
Tobias Platen [Sun, 10 Jan 2021 13:05:03 +0000 (14:05 +0100)]
add microwatt mmu config option to compunits.py