soc.git
4 years agotake out unneeded code, add Settle() to see if it helps with bug
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:59:34 +0000 (22:59 +0100)]
take out unneeded code, add Settle() to see if it helps with bug

4 years agoadd lk field to DecodeOut2
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:52:14 +0000 (22:52 +0100)]
add lk field to DecodeOut2

4 years agomove setting cia input to branch from get_cu_inputs function
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:07:46 +0000 (22:07 +0100)]
move setting cia input to branch from get_cu_inputs function

4 years agohooray, get_cu_inputs now common to both types of tests
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 21:07:25 +0000 (22:07 +0100)]
hooray, get_cu_inputs now common to both types of tests

4 years agooooo very annoying. there does not appear to be any difference between two set_input...
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:57:28 +0000 (21:57 +0100)]
oooo very annoying.  there does not appear to be any difference between two set_inputs functions

4 years agoadd get_inputs function to branch test_pipe_caller
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:36:11 +0000 (21:36 +0100)]
add get_inputs function to branch test_pipe_caller

4 years agoremove unneeded variable
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:35:54 +0000 (21:35 +0100)]
remove unneeded variable

4 years agoRevert "ok ok - for OP_BCREG put CTR in spr2 as well"
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:28:01 +0000 (21:28 +0100)]
Revert "ok ok - for OP_BCREG put CTR in spr2 as well"

This reverts commit 87810631b7ecbd34ad89b2853bbdb763fe003633.

4 years agook ok - for OP_BCREG put CTR in spr2 as well
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:25:50 +0000 (21:25 +0100)]
ok ok - for OP_BCREG put CTR in spr2 as well

4 years agoSelect spr1 for bcctr - use fast_spr decoding from decoder
Michael Nolan [Tue, 2 Jun 2020 20:23:28 +0000 (16:23 -0400)]
Select spr1 for bcctr - use fast_spr decoding from decoder

4 years agoset up CTR and LR only on BCREG when needed
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:18:53 +0000 (21:18 +0100)]
set up CTR and LR only on BCREG when needed

4 years agodecode fast spr for OP_BCREG CTR, TAR and LR
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 20:15:35 +0000 (21:15 +0100)]
decode fast spr for OP_BCREG CTR, TAR and LR

4 years agoadd TODO comments for read_fast1/2
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 19:15:50 +0000 (20:15 +0100)]
add TODO comments for read_fast1/2

4 years agoproof_datamerger: proof that output is zero when idle
Tobias Platen [Tue, 2 Jun 2020 19:13:35 +0000 (21:13 +0200)]
proof_datamerger: proof that output is zero when idle

4 years agoargh overlapping commits on submodule (rebase did not work properly)
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 19:01:38 +0000 (20:01 +0100)]
argh overlapping commits on submodule (rebase did not work properly)
extra commit just to make sure it updates properly

4 years agodebugging branch fast registers
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 18:59:34 +0000 (19:59 +0100)]
debugging branch fast registers

4 years agoFix broken wiki version
Michael Nolan [Tue, 2 Jun 2020 18:42:29 +0000 (14:42 -0400)]
Fix broken wiki version

4 years agoHandle removal of spr2 field from decoder
Michael Nolan [Tue, 2 Jun 2020 18:27:40 +0000 (14:27 -0400)]
Handle removal of spr2 field from decoder

4 years agoadd comment about fast1 and fast2 in branch test_pipe_caller
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 18:26:11 +0000 (19:26 +0100)]
add comment about fast1 and fast2 in branch test_pipe_caller

4 years agoadd regspecmap function to PowerDecode2
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 18:20:52 +0000 (19:20 +0100)]
add regspecmap function to PowerDecode2

4 years agoFix test_bc_reg
Michael Nolan [Tue, 2 Jun 2020 18:10:45 +0000 (14:10 -0400)]
Fix test_bc_reg

4 years agoFix issues with test_bc_reg, wrong instruction field for CR selector
Michael Nolan [Tue, 2 Jun 2020 17:20:23 +0000 (13:20 -0400)]
Fix issues with test_bc_reg, wrong instruction field for CR selector

4 years agomove regspec function to separate module
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 17:39:35 +0000 (18:39 +0100)]
move regspec function to separate module

4 years agoadd in fast regs support in decoder and into regspec_decode
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 17:34:29 +0000 (18:34 +0100)]
add in fast regs support in decoder and into regspec_decode

4 years agoadd 2nd write-reg for LD/ST Update mode
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 17:02:11 +0000 (18:02 +0100)]
add 2nd write-reg for LD/ST Update mode

4 years agoadd write-regs encoding to regspec decoder
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 16:52:42 +0000 (17:52 +0100)]
add write-regs encoding to regspec decoder

4 years agoadd read-write register numbering detection
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 16:32:12 +0000 (17:32 +0100)]
add read-write register numbering detection

4 years agowhoops cut/paste error, creating write_ports not read_ports
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 16:15:16 +0000 (17:15 +0100)]
whoops cut/paste error, creating write_ports not read_ports

4 years agowhoops syntax error
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 15:36:58 +0000 (16:36 +0100)]
whoops syntax error

4 years agoadd function expressing the relationship between regspecs and Decode2Execute1Type
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 14:16:24 +0000 (15:16 +0100)]
add function expressing the relationship between regspecs and Decode2Execute1Type

4 years agowhitespace
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 13:55:12 +0000 (14:55 +0100)]
whitespace

4 years agorename regspecs to give a consistent naming scheme
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 13:54:51 +0000 (14:54 +0100)]
rename regspecs to give a consistent naming scheme
the Decode phase needs to be able to associate regspec information with
actual signals, back in Decode2Execute1Type.  the simplest way to do this
is to make the regspec register names consistent and actually refer
*to* Decode2Execute1Type signals

4 years agoadd MSR constants, TODO translated
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 11:19:32 +0000 (12:19 +0100)]
add MSR constants, TODO translated

4 years agoadd TODO comments from microwatt source code
Luke Kenneth Casson Leighton [Tue, 2 Jun 2020 11:06:42 +0000 (12:06 +0100)]
add TODO comments from microwatt source code

4 years agoAllow at least one operand to be fetched
Cesar Strauss [Tue, 2 Jun 2020 09:37:57 +0000 (06:37 -0300)]
Allow at least one operand to be fetched

We successfully disabled all rel signals. One was immediate, the other was
masked. Let's enable at least one of them, for now.
When the test code is complete, we will be able to issue several
transactions in sequence, with different combinations. We are not there
yet.

4 years agoHold rdmaskn active during the busy_o cycle
Cesar Strauss [Tue, 2 Jun 2020 09:21:50 +0000 (06:21 -0300)]
Hold rdmaskn active during the busy_o cycle

4 years agoremove reading port 3 for CR pipeline. RS moved to port 1
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 22:06:00 +0000 (23:06 +0100)]
remove reading port 3 for CR pipeline.  RS moved to port 1

4 years agookaaay add a "rdflags" function which obtains the yes/no flags for each register...
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 21:39:06 +0000 (22:39 +0100)]
okaaay add a "rdflags" function which obtains the yes/no flags for each register to the CompUnit
this to be used by the Decode phase

4 years agoadd test_bc_reg (fails)
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 20:38:43 +0000 (21:38 +0100)]
add test_bc_reg (fails)

4 years agoremove unneeded fields from Decode2Execute1Type
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 20:25:12 +0000 (21:25 +0100)]
remove unneeded fields from Decode2Execute1Type

4 years agoAdd proof for RegFile
Michael Nolan [Mon, 1 Jun 2020 19:51:43 +0000 (15:51 -0400)]
Add proof for RegFile

4 years agomore unneeded fields from SR InputRecord
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:16:25 +0000 (20:16 +0100)]
more unneeded fields from SR InputRecord

4 years agoremove data_len from SR input record
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:15:06 +0000 (20:15 +0100)]
remove data_len from SR input record

4 years agoremove zero/invert from ShiftRot Input Record
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:14:06 +0000 (20:14 +0100)]
remove zero/invert from ShiftRot Input Record

4 years agoadd shift-rot input record and use it
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:08:21 +0000 (20:08 +0100)]
add shift-rot input record and use it

4 years agoCompBROpSubset exists
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 19:03:03 +0000 (20:03 +0100)]
CompBROpSubset exists

4 years agoRS moved to port 1 (from port 3), remove need in ALU to read/mux into A operand
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:51:54 +0000 (19:51 +0100)]
RS moved to port 1 (from port 3), remove need in ALU to read/mux into A operand

4 years agoAdd proof for RegFileArray
Michael Nolan [Mon, 1 Jun 2020 18:50:52 +0000 (14:50 -0400)]
Add proof for RegFileArray

4 years agoremove use of reg3 in logical pipeline: CSV files moved RS to position 1
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:45:01 +0000 (19:45 +0100)]
remove use of reg3 in logical pipeline: CSV files moved RS to position 1

4 years agoHave regfile use AnySeq instead of AnyConst
Michael Nolan [Mon, 1 Jun 2020 18:40:41 +0000 (14:40 -0400)]
Have regfile use AnySeq instead of AnyConst

4 years agorotator carry is set into both XER CA and CA32 fields
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:13:08 +0000 (19:13 +0100)]
rotator carry is set into both XER CA and CA32 fields

4 years agocomment out rlwinm. for now
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 18:05:38 +0000 (19:05 +0100)]
comment out rlwinm. for now

4 years agoargh - need to zero the src_i input after "Read" is actioned
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 17:57:35 +0000 (18:57 +0100)]
argh - need to zero the src_i input after "Read" is actioned

4 years agoEnable k-induction for register file proof
Michael Nolan [Mon, 1 Jun 2020 17:48:13 +0000 (13:48 -0400)]
Enable k-induction for register file proof

4 years agoThat was weird. For some reason it wasn't generating any ports
Michael Nolan [Mon, 1 Jun 2020 17:46:17 +0000 (13:46 -0400)]
That was weird. For some reason it wasn't generating any ports

4 years agoFull BMC proof of Register
Michael Nolan [Mon, 1 Jun 2020 17:34:44 +0000 (13:34 -0400)]
Full BMC proof of Register

4 years agoBegin rewrite of proof_regfile.py
Michael Nolan [Mon, 1 Jun 2020 17:18:14 +0000 (13:18 -0400)]
Begin rewrite of proof_regfile.py

4 years agoput RB in 2nd position (matching immediate) in ShiftRot Input Data
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 17:39:50 +0000 (18:39 +0100)]
put RB in 2nd position (matching immediate) in ShiftRot Input Data

4 years agosigh - another instance where write-mask needed to mask out wr.rel
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 16:53:31 +0000 (17:53 +0100)]
sigh - another instance where write-mask needed to mask out wr.rel

4 years agoremove xer so/ov, swap rs/rb to correct(?) order in shiftrot test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 16:01:05 +0000 (17:01 +0100)]
remove xer so/ov, swap rs/rb to correct(?) order in shiftrot test

4 years agoproof_datamerger wip
Tobias Platen [Mon, 1 Jun 2020 15:56:21 +0000 (17:56 +0200)]
proof_datamerger wip

4 years agoadd rlwinm. test instruction (sets CR0)
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 15:38:10 +0000 (16:38 +0100)]
add rlwinm. test instruction (sets CR0)

4 years agoremove duplicate signal
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 15:17:48 +0000 (16:17 +0100)]
remove duplicate signal

4 years agoallow ALU / Logical ops to select RS as 1st operand
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 12:36:14 +0000 (13:36 +0100)]
allow ALU / Logical ops to select RS as 1st operand

4 years agoallow M*-Form shiftrot to swap RS/RB back to consistent positions
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 12:27:00 +0000 (13:27 +0100)]
allow M*-Form shiftrot to swap RS/RB back to consistent positions

4 years agoadd first version of ShiftRot CompUnit test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 11:38:45 +0000 (12:38 +0100)]
add first version of ShiftRot CompUnit test

4 years agoshiftrot uses LogicalOutputData not ALUOutputData
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 11:38:25 +0000 (12:38 +0100)]
shiftrot uses LogicalOutputData not ALUOutputData

4 years agoAdd rdmaskn parameter and assert it along issue_i
Cesar Strauss [Mon, 1 Jun 2020 10:56:12 +0000 (07:56 -0300)]
Add rdmaskn parameter and assert it along issue_i

Like zero_a and imm_ok, rdmaskn disallows the activation of go.

4 years agoadd assertions for branch compunit output
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 10:31:45 +0000 (11:31 +0100)]
add assertions for branch compunit output

4 years agoinvert SPR1/2 in branch output data
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 10:29:00 +0000 (11:29 +0100)]
invert SPR1/2 in branch output data

4 years agodecode SPRs for branch
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:50:28 +0000 (05:50 +0100)]
decode SPRs for branch

4 years agoswap over SPR1/2 to fit with microwatt SPR conventions
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:39:25 +0000 (05:39 +0100)]
swap over SPR1/2 to fit with microwatt SPR conventions

4 years agoadd first version compunit branch test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:38:44 +0000 (05:38 +0100)]
add first version compunit branch test

4 years agowhoops need to read RS in CR inputs test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 04:20:08 +0000 (05:20 +0100)]
whoops need to read RS in CR inputs test

4 years agoadd first version of CR CompUnit test
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 03:46:26 +0000 (04:46 +0100)]
add first version of CR CompUnit test

4 years agominor adjustment, zero test in ALU output stage
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 02:25:39 +0000 (03:25 +0100)]
minor adjustment, zero test in ALU output stage

4 years agoremove unneeded code
Luke Kenneth Casson Leighton [Mon, 1 Jun 2020 00:52:50 +0000 (01:52 +0100)]
remove unneeded code

4 years agobit-test on the function-unit value being tested
Luke Kenneth Casson Leighton [Sun, 31 May 2020 23:20:20 +0000 (00:20 +0100)]
bit-test on the function-unit value being tested
this because Function Unit is a bitfield

4 years agoupdate isatables to cmpb not modifying CR0
Luke Kenneth Casson Leighton [Sun, 31 May 2020 23:14:11 +0000 (00:14 +0100)]
update isatables to cmpb not modifying CR0

4 years agoadd logical compunit test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 23:07:42 +0000 (00:07 +0100)]
add logical compunit test

4 years agocomment inputs and outputs from ALU unit test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:50:34 +0000 (19:50 +0100)]
comment inputs and outputs from ALU unit test

4 years agoimports - use of globals. baaaad
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:46:44 +0000 (19:46 +0100)]
imports - use of globals. baaaad

4 years agoremove unneeded code and inputs. convert to "naming" in CompUnit inputs
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:45:12 +0000 (19:45 +0100)]
remove unneeded code and inputs. convert to "naming" in CompUnit inputs

4 years agosplit out common code from test_alu_compunit.py
Luke Kenneth Casson Leighton [Sun, 31 May 2020 18:27:56 +0000 (19:27 +0100)]
split out common code from test_alu_compunit.py

4 years agoadd comments for MultiCompUnit parallel test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 17:03:31 +0000 (18:03 +0100)]
add comments for MultiCompUnit parallel test

4 years agode-hard-code-ify getting results from MultiCompUnit
Luke Kenneth Casson Leighton [Sun, 31 May 2020 16:57:46 +0000 (17:57 +0100)]
de-hard-code-ify getting results from MultiCompUnit

4 years agoremove unneeded imports
Luke Kenneth Casson Leighton [Sun, 31 May 2020 16:44:03 +0000 (17:44 +0100)]
remove unneeded imports

4 years agosplit out compalu unit tests to separate module (getting quite big)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 16:41:28 +0000 (17:41 +0100)]
split out compalu unit tests to separate module (getting quite big)

4 years agoHA! found a bug in MultiCompUnit handling of write-masks
Luke Kenneth Casson Leighton [Sun, 31 May 2020 14:58:04 +0000 (15:58 +0100)]
HA! found a bug in MultiCompUnit handling of write-masks

4 years agoclarify
Luke Kenneth Casson Leighton [Sun, 31 May 2020 13:35:17 +0000 (14:35 +0100)]
clarify

4 years agoOP_CMPEQB also requesting change of output reg (stop that)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 13:34:09 +0000 (14:34 +0100)]
OP_CMPEQB also requesting change of output reg (stop that)

4 years agoOP_CMP is requesting a change of the output register (should not do that)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 13:26:21 +0000 (14:26 +0100)]
OP_CMP is requesting a change of the output register (should not do that)

4 years agostill investigating
Luke Kenneth Casson Leighton [Sun, 31 May 2020 12:19:35 +0000 (13:19 +0100)]
still investigating

4 years agostart with zero, try not to compare against 9 bytes in a 64-bit value: cmpeqb test
Luke Kenneth Casson Leighton [Sun, 31 May 2020 12:08:22 +0000 (13:08 +0100)]
start with zero, try not to compare against 9 bytes in a 64-bit value: cmpeqb test

4 years agomore debug statements
Luke Kenneth Casson Leighton [Sun, 31 May 2020 12:04:13 +0000 (13:04 +0100)]
more debug statements

4 years agoadd in more CR debug statements
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:54:53 +0000 (12:54 +0100)]
add in more CR debug statements

4 years agocopy in cr0.data into cr0 temp, not whole of cr0 (including ok flag)
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:54:29 +0000 (12:54 +0100)]
copy in cr0.data into cr0 temp, not whole of cr0 (including ok flag)

4 years agoremove commented-out vars from ALU input record
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:33:30 +0000 (12:33 +0100)]
remove commented-out vars from ALU input record

4 years agowrite cr0 when op.write_cr.ok is set
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:28:38 +0000 (12:28 +0100)]
write cr0 when op.write_cr.ok is set

4 years agoadd write_cr to ALU record subset
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:27:45 +0000 (12:27 +0100)]
add write_cr to ALU record subset