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Wesley W. Terpstra [Thu, 29 Jun 2017 00:46:45 +0000 (17:46 -0700)]
spi: include mem region (#23)
Wesley W. Terpstra [Thu, 29 Jun 2017 00:45:18 +0000 (17:45 -0700)]
diplomacy: add reg-names to devices (#22)
Megan Wachs [Mon, 19 Jun 2017 19:41:38 +0000 (12:41 -0700)]
gpio: Make IOF optional (#21)
* gpio: Make IOF optional
* IOF: Make the default false
Henry Cook [Thu, 15 Jun 2017 02:47:56 +0000 (19:47 -0700)]
make some base bundle classes easier to clone (#20)
Wesley W. Terpstra [Thu, 15 Jun 2017 00:06:55 +0000 (17:06 -0700)]
spi: add dts ranges field for memory mapped spi (#19)
Henry Cook [Tue, 13 Jun 2017 22:52:11 +0000 (15:52 -0700)]
Merge pull request #18 from sifive/lazy-raw-module-imp
periphery: convert bundle traits
Megan Wachs [Tue, 13 Jun 2017 18:00:29 +0000 (11:00 -0700)]
More Peripheral-to-pins cleanups
Megan Wachs [Tue, 13 Jun 2017 01:08:35 +0000 (18:08 -0700)]
UART: actually return the pins, not just the module. We should do this for the other peripherals as well
Megan Wachs [Tue, 13 Jun 2017 00:53:51 +0000 (17:53 -0700)]
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
Megan Wachs [Tue, 13 Jun 2017 00:53:08 +0000 (17:53 -0700)]
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
Henry Cook [Mon, 5 Jun 2017 21:33:53 +0000 (14:33 -0700)]
periphery: convert periphery bundle traits to work with system-level multi-io module
Megan Wachs [Sat, 10 Jun 2017 05:07:43 +0000 (22:07 -0700)]
Merge pull request #17 from sifive/peripheral_options
Make more peripherals "listable" to allow for 0 or more
Megan Wachs [Fri, 9 Jun 2017 20:53:22 +0000 (13:53 -0700)]
peripheral_options: Actually compiles
Megan Wachs [Thu, 8 Jun 2017 23:29:01 +0000 (16:29 -0700)]
SPIFlash: make it listable
Megan Wachs [Thu, 8 Jun 2017 23:25:20 +0000 (16:25 -0700)]
GPIO: Make GPIO peripheral another listable one
Wesley W. Terpstra [Fri, 2 Jun 2017 22:56:18 +0000 (15:56 -0700)]
vc707axi: track rocketchip API changes (#16)
Wesley W. Terpstra [Sun, 14 May 2017 06:38:20 +0000 (23:38 -0700)]
uart: power-on with the right divider for the design (#15)
Wesley W. Terpstra [Sat, 13 May 2017 06:15:14 +0000 (23:15 -0700)]
Merge pull request #14 from sifive/async-pcie
Async PCIe
Wesley W. Terpstra [Sat, 13 May 2017 06:07:10 +0000 (23:07 -0700)]
vc707mig: use an external ibuf
This makes it possible to also drive a PLL of our own from the crystal.
Wesley W. Terpstra [Sat, 13 May 2017 05:59:48 +0000 (22:59 -0700)]
xilinxvc707pciex1: push to a dedicated clock domain
Wesley W. Terpstra [Thu, 11 May 2017 18:50:07 +0000 (11:50 -0700)]
xilinx mig: put a buffer infront of the controller (#13)
This makes placement of the L2 and DDR controller easier.
Wesley W. Terpstra [Mon, 8 May 2017 08:08:37 +0000 (01:08 -0700)]
xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)
Henry Cook [Wed, 3 May 2017 18:46:30 +0000 (11:46 -0700)]
Merge pull request #10 from sifive/axi-mmio
axi4: switch to new pipelined converters
Yunsup Lee [Tue, 2 May 2017 21:36:39 +0000 (14:36 -0700)]
Merge pull request #11 from sifive/spi
SPI errata fixes
Albert Ou [Tue, 2 May 2017 19:35:34 +0000 (12:35 -0700)]
spi: Fix off-by-one error in calculating cycles per data frame
Issue: Configuring the frame length to certain values causes incorrect
operation.
Symptoms: Certain frame lengths result in the master sending one extra
clock pulse. The slave device may then become desynchronized.
Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
* Serial mode: 0, 2, 4, 6, 8
* Dual mode: 0, 1, 3, 5, 7, 8
* Quad mode: 0, 1, 2, 3, 5, 6, 7, 8
Albert Ou [Tue, 2 May 2017 19:07:37 +0000 (12:07 -0700)]
spi: Fix io.port.dq(3) output enable
Issue: The output enable signal for DQ[3] is not driven properly.
Symptoms: Output data from master to slave is not properly transmitted
in quad mode. Data received from the slave is unaffected.
Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol. Do not use the Native Quad SPI protocol.
Wesley W. Terpstra [Wed, 26 Apr 2017 20:10:50 +0000 (13:10 -0700)]
axi4: switch to new pipelined converters
Henry Styles [Tue, 25 Apr 2017 17:18:46 +0000 (10:18 -0700)]
Merge pull request #9 from sifive/vc707_mig_analog_inout
Use _chisel3 analog for MIG inout
Henry Styles [Tue, 25 Apr 2017 17:15:00 +0000 (10:15 -0700)]
Use _chisel3 analog for MIG inout
solomatnikov [Tue, 25 Apr 2017 16:14:00 +0000 (09:14 -0700)]
Added stall for read after write (#8)
Megan Wachs [Mon, 10 Apr 2017 21:25:08 +0000 (14:25 -0700)]
Merge pull request #7 from sifive/ndreset
MockAON: Accept the non-debug interrupt as an input to overall reset.
Megan Wachs [Fri, 7 Apr 2017 23:42:32 +0000 (16:42 -0700)]
MockAON: Accept the non-debug interrupt as an input to overall reset.
Megan Wachs [Fri, 31 Mar 2017 22:14:35 +0000 (15:14 -0700)]
Merge pull request #6 from sifive/debug_v013
Debug v013
Megan Wachs [Fri, 31 Mar 2017 20:49:34 +0000 (13:49 -0700)]
spi: correct polarity of FIRRTL combo loop detection workaround.
Megan Wachs [Fri, 31 Mar 2017 03:01:30 +0000 (20:01 -0700)]
Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD
Jack Koenig [Fri, 31 Mar 2017 02:12:15 +0000 (19:12 -0700)]
"Fix" false combinational loop through SPIArbiter
Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
Megan Wachs [Tue, 28 Mar 2017 01:48:24 +0000 (18:48 -0700)]
Merge remote-tracking branch 'origin/master' into debug-0.13
Yunsup Lee [Sat, 25 Mar 2017 04:38:31 +0000 (21:38 -0700)]
rename l2FrontendBus as fsb
Yunsup Lee [Sat, 25 Mar 2017 04:38:31 +0000 (21:38 -0700)]
rename l2FrontendBus as fsb
Megan Wachs [Sat, 25 Mar 2017 00:27:55 +0000 (17:27 -0700)]
JTAG: make TRSTn optional for all helpers as well to match the IO.
Megan Wachs [Thu, 23 Mar 2017 02:16:20 +0000 (19:16 -0700)]
Merge remote-tracking branch 'origin/master' into debug-0.13
Yunsup Lee [Wed, 22 Mar 2017 05:12:37 +0000 (22:12 -0700)]
update TLRegisterNode to take Seq of AddressSet
Megan Wachs [Wed, 22 Mar 2017 00:51:28 +0000 (17:51 -0700)]
TLSPI: address parameter must now be a sequence.
Megan Wachs [Tue, 14 Mar 2017 21:52:39 +0000 (14:52 -0700)]
Adjust JTAG for rocket-chip changes
Megan Wachs [Fri, 10 Mar 2017 22:09:24 +0000 (14:09 -0800)]
Merge remote-tracking branch 'origin/master' into debug-0.13
Wesley W. Terpstra [Fri, 3 Mar 2017 05:22:41 +0000 (21:22 -0800)]
xilinx pcie: add the high PCIe address bits (physical path)
The format is taken from here:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
Wesley W. Terpstra [Fri, 3 Mar 2017 05:00:44 +0000 (21:00 -0800)]
Merge pull request #4 from sifive/periphery-keys
DTS
Wesley W. Terpstra [Fri, 3 Mar 2017 04:28:38 +0000 (20:28 -0800)]
devices: include DTS meta-data
Wesley W. Terpstra [Thu, 23 Feb 2017 02:42:47 +0000 (18:42 -0800)]
devices: create periphery keys for all devices
Standardize how they are connected to the periphery bus
Megan Wachs [Thu, 2 Mar 2017 22:46:34 +0000 (14:46 -0800)]
jtag: The jtag interfaces have moved to a different package.
Megan Wachs [Fri, 17 Feb 2017 02:45:48 +0000 (18:45 -0800)]
Merge pull request #2 from sifive/homogenous_bag_peripherals
Use HeterogenousBag to handle lists of peripherals
Megan Wachs [Fri, 17 Feb 2017 01:52:24 +0000 (17:52 -0800)]
Use HomogenousBag to handle lists of peripherals
Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
solomatnikov [Fri, 10 Feb 2017 22:30:01 +0000 (14:30 -0800)]
Merge pull request #1 from sifive/i2c
I2c implementation
Alex Solomatnikov [Fri, 10 Feb 2017 02:45:35 +0000 (18:45 -0800)]
Merge remote-tracking branch 'origin/master' into i2c
Alex Solomatnikov [Thu, 9 Feb 2017 19:37:40 +0000 (11:37 -0800)]
Flipped polarity of output enables to match Guava pins logic
Alex Solomatnikov [Thu, 9 Feb 2017 19:36:19 +0000 (11:36 -0800)]
Made regs 32-bit word aligned to match the rest of the system
Alex Solomatnikov [Wed, 8 Feb 2017 00:14:28 +0000 (16:14 -0800)]
Added note: WISHBONE interface replaced by Tilelink2
Alex Solomatnikov [Tue, 7 Feb 2017 23:58:04 +0000 (15:58 -0800)]
Added license
Alex Solomatnikov [Mon, 6 Feb 2017 18:39:47 +0000 (10:39 -0800)]
Renamed i2cDevices to i2c
Wesley W. Terpstra [Sat, 4 Feb 2017 02:17:58 +0000 (18:17 -0800)]
xilinx mig: track changes in rocket-chip
Alex Solomatnikov [Sat, 4 Feb 2017 02:10:03 +0000 (18:10 -0800)]
Addressing comments: bool style, comments, removed suggestName
Alex Solomatnikov [Sat, 4 Feb 2017 00:41:59 +0000 (16:41 -0800)]
Bug fixes: passing OC WB test
Wesley W. Terpstra [Wed, 1 Feb 2017 21:53:54 +0000 (13:53 -0800)]
sifive-blocks: trust diplomacy to get names right
Alex Solomatnikov [Wed, 1 Feb 2017 01:20:53 +0000 (17:20 -0800)]
Completed Chisel RTL (not tested yet)
Wesley W. Terpstra [Tue, 31 Jan 2017 22:03:14 +0000 (14:03 -0800)]
spi: work around ucb-bar/chisel3#472
Wesley W. Terpstra [Mon, 30 Jan 2017 19:33:30 +0000 (11:33 -0800)]
xilinx ip: adjust to new diplomacy API
Alex Solomatnikov [Tue, 24 Jan 2017 22:58:01 +0000 (14:58 -0800)]
Initial (compilable) version of I2C (no actual logic yet)
Wesley W. Terpstra [Sat, 21 Jan 2017 06:38:27 +0000 (22:38 -0800)]
xilinx pcie: put buffers before the outputs to the controller
Wesley W. Terpstra [Fri, 20 Jan 2017 03:53:03 +0000 (19:53 -0800)]
mig: track change to Blind port API in rocket
Wesley W. Terpstra [Wed, 7 Dec 2016 21:21:20 +0000 (13:21 -0800)]
LazyModule: provide Parameters
This tracks PR #478 in rocketchip.
Wesley W. Terpstra [Wed, 7 Dec 2016 00:13:12 +0000 (16:13 -0800)]
xilinx pcie: bytes, not bits
This bug amazingly compiled correctly and ran correctly!
It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.
The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
Wesley W. Terpstra [Sat, 3 Dec 2016 01:48:17 +0000 (17:48 -0800)]
RegMapFIFO: amoor.w can do thread-safe TX
Richard Xia [Wed, 30 Nov 2016 21:29:54 +0000 (13:29 -0800)]
Add /target to .gitignore.
SiFive [Tue, 29 Nov 2016 12:08:44 +0000 (04:08 -0800)]
Initial commit.