Tim Newsome [Wed, 8 Aug 2018 21:33:50 +0000 (14:33 -0700)]
Add jump/hbreak test.
Andrew Waterman [Mon, 9 Jul 2018 21:25:46 +0000 (14:25 -0700)]
Check that SC yields the load reservation
https://github.com/riscv/riscv-isa-manual/commit/
03a5e722fc0fe7b94dd0a49f550ff7b41a63f612
Tim Newsome [Tue, 3 Jul 2018 20:54:13 +0000 (13:54 -0700)]
rwatch/watch on explicit address
Newer gdb requires more debug info in order to "watch data" in this
test. I'm not sure how to make that debug info happen, so instead we
tell it the address to use.
Tim Newsome [Mon, 18 Jun 2018 22:03:05 +0000 (15:03 -0700)]
Add reproduce line to the end of debug test logs
Tim Newsome [Mon, 21 May 2018 18:56:39 +0000 (11:56 -0700)]
Merge pull request #141 from riscv/mrhstest
Fix MulticoreRunHaltStepiTest
Tim Newsome [Sat, 19 May 2018 01:12:00 +0000 (18:12 -0700)]
Fix MulticoreRunHaltStepiTest
The test actually wasn't checking interrupt counts at all. Fixing it
required some other changes:
Make sure all harts get to run
Add some retries, since on a loaded machine against spike both harts
might not get to run, even if you give spike a generous amount of time
to do so.
Megan Wachs [Tue, 15 May 2018 17:19:08 +0000 (10:19 -0700)]
Merge pull request #139 from riscv/debug-tests-more-single
Mark more Debug tests as "Single Hart"
Megan Wachs [Mon, 14 May 2018 23:04:10 +0000 (16:04 -0700)]
Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single
Tim Newsome [Mon, 14 May 2018 22:14:47 +0000 (15:14 -0700)]
Make DownloadTest properly park other harts.
Megan Wachs [Mon, 14 May 2018 21:34:58 +0000 (14:34 -0700)]
debug: remove some unintentionally added newlines
Megan Wachs [Mon, 14 May 2018 15:46:03 +0000 (08:46 -0700)]
debug: Fixing the non-RTOS behavior for DownloadTest
Megan Wachs [Fri, 11 May 2018 16:40:10 +0000 (09:40 -0700)]
debug: mark more tests as single-hart tests
Megan Wachs [Fri, 11 May 2018 16:39:48 +0000 (09:39 -0700)]
debug: output some more useful info into the post-mortem data
Christopher Celio [Tue, 1 May 2018 00:03:50 +0000 (17:03 -0700)]
[rv64ua/lrsc] Initialize memory read out. (#135)
* [rv64ua/lrsc] Initialize memory read out.
Even though the load contents are discarded, this un-initialized memory value
can lead to a divergence for co-simulation between two different RISC-V designs.
* [rv64ua/lrsc] Use .skip instead of .align.
Tim Newsome [Mon, 30 Apr 2018 19:54:03 +0000 (12:54 -0700)]
Fix formatting to make pylint happy.
Megan Wachs [Sun, 29 Apr 2018 03:38:37 +0000 (20:38 -0700)]
Merge pull request #132 from riscv/debug-clear-satp
debug: need to clear satp before changing priv
Megan Wachs [Fri, 27 Apr 2018 23:52:43 +0000 (16:52 -0700)]
debug: need to clear satp before changing priv
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.
Megan Wachs [Fri, 27 Apr 2018 22:18:57 +0000 (15:18 -0700)]
Merge pull request #125 from riscv/debug-delete-sim
Delete E300Sim.py
Megan Wachs [Fri, 27 Apr 2018 22:18:44 +0000 (15:18 -0700)]
Merge pull request #130 from riscv/trap_entry_align-1
debug: add missing align directive on trap_entry
Megan Wachs [Fri, 27 Apr 2018 21:42:34 +0000 (14:42 -0700)]
debug: add missing align directive on trap_entry
Tim Newsome [Tue, 24 Apr 2018 18:21:27 +0000 (11:21 -0700)]
Fix race when making logs directory
Megan Wachs [Thu, 19 Apr 2018 17:46:23 +0000 (10:46 -0700)]
Delete E300Sim.py
This file is wrong (the .cfg file isn't right) and not used by anything.
Tim Newsome [Mon, 16 Apr 2018 19:14:13 +0000 (12:14 -0700)]
Merge pull request #123 from riscv/gdb_timeout
Compute gdb command timeout based on ops estimate
Tim Newsome [Mon, 9 Apr 2018 20:09:55 +0000 (13:09 -0700)]
Compute gdb command timeout based on ops estimate
The caller of gdb.command() should estimate how much work gdb needs to
do, and testlib then scales this up proportional to the general gdb
timeout we configured. This hopefully allows us to configure a tighter
timeout, so we don't have to have a multi-hour timeout just for
something that takes long like `load` on a really slow simulator.
Hopefully this addresses #122.
Andrei Tatarnikov [Mon, 9 Apr 2018 18:24:04 +0000 (21:24 +0300)]
Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121)
Tim Newsome [Mon, 2 Apr 2018 21:56:45 +0000 (14:56 -0700)]
Use `gdb_report_register_access_error enable`
Tim Newsome [Tue, 27 Feb 2018 22:28:26 +0000 (14:28 -0800)]
Test debug authentication.
Also halt instead of reset spike targets, which tests a more complicated
code path.
Tim Newsome [Fri, 23 Mar 2018 20:27:52 +0000 (13:27 -0700)]
Print log filename at the end of the log.
This makes it much easier to look at a log if you see a failure
scrolling by on your terminal.
Andrew Waterman [Wed, 21 Mar 2018 23:54:08 +0000 (16:54 -0700)]
Make misa.C test conform to Hauser proposal
See https://github.com/riscv/riscv-isa-manual/commit/
0472bcdd166f45712492829a250e228bb45fa5e7
Palmer Dabbelt [Wed, 21 Mar 2018 01:14:18 +0000 (18:14 -0700)]
Merge pull request #119 from rishikhan/master
Update Makefile to allow for RISCV_PREFIX to be set by the configure
rishi [Mon, 19 Mar 2018 16:02:53 +0000 (12:02 -0400)]
Update Makefile to allow for RISCV_PREFIX to be set by the configure --target
Tim Newsome [Mon, 19 Feb 2018 21:31:40 +0000 (13:31 -0800)]
Test debugging with/without a program buffer
Tim Newsome [Thu, 1 Mar 2018 23:05:45 +0000 (15:05 -0800)]
Ensure an error when reading a non-existent CSR.
Andrew Waterman [Tue, 27 Feb 2018 07:25:34 +0000 (01:25 -0600)]
Add test for clearing misa.C while PC is misaligned (#117)
See https://github.com/riscv/riscv-isa-manual/pull/139
Tim Newsome [Fri, 9 Feb 2018 16:54:59 +0000 (08:54 -0800)]
Test resuming from a trigger.
Tim Newsome [Wed, 7 Feb 2018 21:48:54 +0000 (13:48 -0800)]
Link scripts shouldn't be executable.
Tim Newsome [Mon, 8 Jan 2018 20:36:49 +0000 (12:36 -0800)]
Deal with gdb reporting pmpcfg0 not existing.
It's an optional register.
Tim Newsome [Fri, 5 Jan 2018 22:25:57 +0000 (14:25 -0800)]
Add test for multicore failure
Specifically, make sure that after resuming all cores, and halting core
0, that OpenOCD's poll() doesn't mess up the currently selected hart to
the point where memory accesses intended for core 0 go to core 1.
Andrew Waterman [Wed, 3 Jan 2018 05:13:38 +0000 (21:13 -0800)]
Test access exception behavior for illegal addresses (#111)
OK'd by @palmer-dabbelt
Tim Newsome [Wed, 27 Dec 2017 23:41:45 +0000 (15:41 -0800)]
Test FPRs that aren't XLEN in size.
Cover all combinations of 32,64 bit XLEN with F and FD extensions.
Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
Tim Newsome [Fri, 22 Dec 2017 00:00:01 +0000 (16:00 -0800)]
Add all-tests target.
I hope to use this in riscv-tools' regression.sh.
Megan Wachs [Thu, 21 Dec 2017 23:35:15 +0000 (15:35 -0800)]
Merge pull request #110 from riscv/bump_env
tests: bump env to pick up new names for CSRs
Megan Wachs [Thu, 21 Dec 2017 23:23:38 +0000 (15:23 -0800)]
tests: bump env to pick up new names for CSRs
Tim Newsome [Wed, 20 Dec 2017 23:00:01 +0000 (15:00 -0800)]
Remove `set arch riscv:rv%d`
gdb gets target XLEN from register width now, so this is taken care of
automatically.
Tim Newsome [Wed, 20 Dec 2017 20:17:05 +0000 (12:17 -0800)]
Verify that F18 does not exist on FPU-less targets
Tim Newsome [Tue, 12 Dec 2017 16:02:38 +0000 (08:02 -0800)]
Display env variables used when invoking OpenOCD
This makes it a little easier to just cut and paste from the log when
reproducing a failure. (The port number still needs changing though.)
Tim Newsome [Fri, 1 Dec 2017 22:29:11 +0000 (14:29 -0800)]
Ensure there are no unnamed registers.
Tim Newsome [Thu, 30 Nov 2017 20:24:32 +0000 (12:24 -0800)]
Merge pull request #109 from riscv/vcssim
Clean up VcsSim init()
Tim Newsome [Thu, 30 Nov 2017 19:50:18 +0000 (11:50 -0800)]
Clean up VcsSim init()
Use a unique log file, so you can run multiple instances at once.
Add time out to waiting for the simulator to be ready.
Andrew Waterman [Mon, 27 Nov 2017 22:37:58 +0000 (14:37 -0800)]
Rename sbadaddr to satp
Torbjørn [Mon, 27 Nov 2017 05:56:53 +0000 (06:56 +0100)]
Rv32ud tests (#108)
* Probably implemented the changes required to support fadd test for rv32ud
* Created test files in rv32ud, implemented working(?) test for ldst
* fclass, fcvt_w, fmin and recoding seem to be working now
* Got fdiv (and sqrt) tests working
* fmadd tests seem to work
* fcmp works
* [WIP] fcvt working, but lacks a 32-bit implementation of the final test
* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST
* Added Makefrag for rv32ud tests and included in main isa Makefile
* Don't run 64-bit tests if the defined XLEN is 32
Christopher Celio [Wed, 22 Nov 2017 22:01:26 +0000 (14:01 -0800)]
Check sepc for rv64si/scall test. (#107)
Closes #105.
Andrew Waterman [Mon, 20 Nov 2017 19:59:28 +0000 (11:59 -0800)]
Check mtval in rv64mi-p-illegal (#104)
Closes #103
Tim Newsome [Mon, 20 Nov 2017 04:54:33 +0000 (20:54 -0800)]
Ensure log file is fully written before reading it
Fixes --print-failures sometimes not actually printing out details about
failures.
Tim Newsome [Mon, 20 Nov 2017 04:54:14 +0000 (20:54 -0800)]
Make pylint happy.
Megan Wachs [Fri, 17 Nov 2017 21:43:33 +0000 (13:43 -0800)]
Merge pull request #102 from riscv/xlen_fix
debug: Fix the XLEN command line check
Megan Wachs [Fri, 17 Nov 2017 19:27:04 +0000 (11:27 -0800)]
debug: Fix the XLEN command line check
Megan Wachs [Fri, 17 Nov 2017 00:34:02 +0000 (16:34 -0800)]
Debug: Use the --32 and --64 command line arguments (#97)
* Debug: Actually use the --32 and --64 command line arguments
* debug: make XLEN mismatch message clearer
Tim Newsome [Thu, 16 Nov 2017 23:40:27 +0000 (15:40 -0800)]
Disable PMP for PrivRw test.
Tim Newsome [Thu, 16 Nov 2017 00:51:49 +0000 (16:51 -0800)]
Clarify PrivTest detail.
Andrew Waterman [Sun, 12 Nov 2017 00:15:22 +0000 (16:15 -0800)]
Make sure that code is 4-byte aligned before disabling rvc (#100)
Andrew Waterman [Fri, 10 Nov 2017 03:25:22 +0000 (19:25 -0800)]
Make rv64mi-p-ecall work when U-mode is not present
Andrew Waterman [Fri, 10 Nov 2017 01:12:49 +0000 (17:12 -0800)]
Use mstatus.MPP to check existence of U-mode
misa is allowed to be hardwired to 0, so checking its U bit could
incorrectly suggest that U-mode is not supported.
Tim Newsome [Thu, 2 Nov 2017 22:14:40 +0000 (15:14 -0700)]
Add --print-log-names to print temp log names ASAP
When not passed, they are no longer printed out.
Tim Newsome [Thu, 2 Nov 2017 20:11:50 +0000 (13:11 -0700)]
Ensure gdb connection failures end up in main log.
Megan Wachs [Thu, 2 Nov 2017 15:46:24 +0000 (08:46 -0700)]
debug: Need to apply remotetimeout before connecting to remote target (#94)
* debug: Need to apply remotetimeout before connecting to remote target
* debug: whitespace cleanup
Christopher Celio [Wed, 1 Nov 2017 20:46:34 +0000 (13:46 -0700)]
SBREAK test now checks EPC value. (#92)
Closes #89
Tim Newsome [Wed, 1 Nov 2017 19:36:36 +0000 (12:36 -0700)]
Make pylint 1.6.5 happy.
Tim Newsome [Wed, 1 Nov 2017 19:19:16 +0000 (12:19 -0700)]
Test register aliases in the simple register tests
Tim Newsome [Wed, 1 Nov 2017 18:43:04 +0000 (11:43 -0700)]
Fix MulticoreRegTest.
This test would fail intermittently if gdb on the first hart managed to
set a breakpoint, resume, halt, and clear the breakpoint before the
second hart got a chance to resume.
Palmer Dabbelt [Tue, 31 Oct 2017 23:07:21 +0000 (16:07 -0700)]
Merge pull request #90 from richardxia/comment-out-multicore-reg-test
Temporarily comment out MulticoreRegTest due to flakiness.
Richard Xia [Tue, 31 Oct 2017 20:19:21 +0000 (13:19 -0700)]
Temporarily comment out MulticoreRegTest due to flakiness.
Richard Xia [Mon, 30 Oct 2017 22:44:21 +0000 (15:44 -0700)]
Remove cache miss test from last AMO test. (#88)
Follow-up to
b68b39031a730ecc155ed87fba2ed5f111d0ab07.
The 64KiB allocated by the code to force a cache miss makes it impossible to run
the test from any memories that are smaller 64KiB, such as scratchpad memories
or LIMs. Since this is trying to test microarchitectural behavior, they don't
belong in these ISA tests anyway.
Richard Xia [Mon, 30 Oct 2017 19:18:49 +0000 (12:18 -0700)]
Declare trap handlers as global symbols. (#87)
This allows them to be referenced by other files, such as a test environment
that lives in a separate compilation unit.
Andrew Waterman [Wed, 20 Sep 2017 17:47:11 +0000 (10:47 -0700)]
Verify that mtval/stval is written correctly on misaligned fetch
Richard Xia [Fri, 27 Oct 2017 04:33:49 +0000 (21:33 -0700)]
Fix rv64mi-csr for the case where U-mode is not available. (#86)
Tim Newsome [Tue, 24 Oct 2017 18:55:01 +0000 (11:55 -0700)]
Increase dual-core RV64 timeouts.
I need this for CompareSections to pass when I instrument spike to be
really slow.
Tim Newsome [Thu, 19 Oct 2017 20:21:26 +0000 (13:21 -0700)]
Get helpful gdb output in MemTestBlock.
Tim Newsome [Thu, 12 Oct 2017 18:53:22 +0000 (11:53 -0700)]
Pay attention to server_timeout_sec
Fixes #83.
Tim Newsome [Sat, 30 Sep 2017 21:48:15 +0000 (14:48 -0700)]
Resurrect priv tests.
Tim Newsome [Wed, 4 Oct 2017 19:40:30 +0000 (12:40 -0700)]
Merge pull request #79 from riscv/multigdb
Multigdb support
Tim Newsome [Fri, 29 Sep 2017 22:41:30 +0000 (15:41 -0700)]
Make ExamineTarget multi-core aware.
Now on multi-core targets it only runs once, wasting less time.
Tim Newsome [Fri, 29 Sep 2017 20:20:30 +0000 (13:20 -0700)]
Fix tests to work in multi-gdb mode.
The Gdb class now can handle connecting to more than one gdb. It
enumerates the harts across all connections, and when asked to select a
hart, it transparently sends future gdb commands to the correct
instance.
Multicore tests still have to be aware of some differences. The main one
is that when executing 'c' in RTOS mode, all harts resume, while in
multi-gdb mode only the current one resumes. Additionally, gdb doesn't
set breakpoints until 'c' is issued, so the hart where breakpoints are
set needs to be resumed before other harts might see them.
Tim Newsome [Fri, 22 Sep 2017 19:57:51 +0000 (12:57 -0700)]
Remove unused function.
Tim Newsome [Thu, 21 Sep 2017 22:19:47 +0000 (15:19 -0700)]
Add coverage for single-core non-rtos OpenOCD.
Tim Newsome [Wed, 20 Sep 2017 00:10:36 +0000 (17:10 -0700)]
Allow multiple reset vectors.
Some boards have jumpers that control the reset vector, and forcing them
one way or another is more annoying than dealing with it in software.
Andrew Waterman [Tue, 19 Sep 2017 21:34:42 +0000 (14:34 -0700)]
Link against libm for fma()
Tim Newsome [Tue, 19 Sep 2017 21:12:12 +0000 (14:12 -0700)]
Merge pull request #76 from riscv/multicore
Add interrupts to MulticoreRunHaltStepiTest.
Tim Newsome [Tue, 19 Sep 2017 18:23:35 +0000 (11:23 -0700)]
Forgot to commit this earlier.
Fixes #77.
Tim Newsome [Mon, 18 Sep 2017 18:31:08 +0000 (11:31 -0700)]
Add interrupts to MulticoreRunHaltStepiTest.
Just to hammer on anything at once, and hopefully catch weird
interactions if they exist.
Tim Newsome [Fri, 15 Sep 2017 19:03:52 +0000 (12:03 -0700)]
Don't read entire log into RAM just to print it.
Tim Newsome [Thu, 14 Sep 2017 23:26:51 +0000 (16:26 -0700)]
misa is stored in the hart now, not the target
Tim Newsome [Thu, 14 Sep 2017 19:59:08 +0000 (12:59 -0700)]
When spike fails to launch, display its output.
Tim Newsome [Wed, 13 Sep 2017 01:48:44 +0000 (18:48 -0700)]
Test debugging code with interrupts.
Tim Newsome [Tue, 12 Sep 2017 18:21:06 +0000 (11:21 -0700)]
Call postMortem() when a test fails.
Tim Newsome [Tue, 12 Sep 2017 18:20:27 +0000 (11:20 -0700)]
Clarify timeout units.
Andrew Waterman [Thu, 14 Sep 2017 18:11:44 +0000 (11:11 -0700)]
Move link options to end of gcc command line
Tim Newsome [Tue, 12 Sep 2017 16:36:34 +0000 (09:36 -0700)]
Merge pull request #69 from riscv/multicore
Proper multicore support for debug tests
Andrew Waterman [Fri, 1 Sep 2017 18:15:44 +0000 (11:15 -0700)]
Improve ma_fetch test to cover JAL and branches
Tim Newsome [Fri, 1 Sep 2017 19:31:15 +0000 (12:31 -0700)]
Add some infrastructure for multicore tests.
When compiling, define the number of harts. This means we only need to
allocate a lot of stack if there are a lot of harts.