Cesar Strauss [Mon, 22 Feb 2021 21:29:11 +0000 (18:29 -0300)]
Fix typo when calculating PowerDecoder2.no_out_vec
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:21:26 +0000 (16:21 +0000)]
move setting of NIA into fetch FSM in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 16:00:24 +0000 (16:00 +0000)]
whoops
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 15:59:33 +0000 (15:59 +0000)]
moving PC-setting (NIA) out of execute_fsm in TestIssuer
Luke Kenneth Casson Leighton [Mon, 22 Feb 2021 14:48:46 +0000 (14:48 +0000)]
rename inter-FSM handshake signals in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:27:06 +0000 (19:27 +0000)]
err trying to put in some FSM handshake signals, getting confused
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:38 +0000 (19:20 +0000)]
comment for where SVSTATE FSM should go
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 19:20:17 +0000 (19:20 +0000)]
add CR out vector detection to PowerDecoder2 no_out_vec
Cesar Strauss [Sun, 21 Feb 2021 17:21:54 +0000 (14:21 -0300)]
The field selection function was moved to nmutil.util
All previous users were updated.
Cesar Strauss [Sun, 21 Feb 2021 17:18:15 +0000 (14:18 -0300)]
Hide the register augmentation traces by default
This saves some vertical space if you are not interested in seeing this
level of detail, but it is still there if you need it.
Needs the latest nmutil version for it to work.
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:50:31 +0000 (15:50 +0000)]
move execute_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:41:08 +0000 (15:41 +0000)]
move fetch_fsm to separate function in TestIssuer
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 15:22:28 +0000 (15:22 +0000)]
add JTAG enable/disable of 4k SRAMs
Cesar Strauss [Sun, 21 Feb 2021 14:50:21 +0000 (11:50 -0300)]
The new version of "sel" is smart enough to find a suitable Signal name
An up-to-date version of nmutil is required for this.
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 13:08:32 +0000 (13:08 +0000)]
add comments for Mode field in SVP64Asm
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 12:58:19 +0000 (12:58 +0000)]
comments in SVP64RMFields
Cesar Strauss [Sun, 21 Feb 2021 12:54:20 +0000 (09:54 -0300)]
Use the new selection field function from nmutil
Note that the new function accepts a Module on which it to generate its
wires, and returns a Signal of the appropriate size.
Be sure to update nmutil to get the new function.
Cesar Strauss [Sun, 21 Feb 2021 09:58:54 +0000 (06:58 -0300)]
Use symbolic values as field sizes
Cesar Strauss [Sat, 20 Feb 2021 23:00:02 +0000 (20:00 -0300)]
Replace all hardcoded shifts into RM by usage of SVP64RMFields
Luke Kenneth Casson Leighton [Sun, 21 Feb 2021 01:04:50 +0000 (01:04 +0000)]
create SVP64CROffs consts for when SVP64 Vector-of-CRs is active (Rc=1)
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:38:17 +0000 (23:38 +0000)]
comments on sv.add. Rc=1 unit test
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:32:50 +0000 (23:32 +0000)]
add in Vectorised CRs when Rc=1 into ISACaller
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 23:15:06 +0000 (23:15 +0000)]
add CR1 to DecodeCRIn/Out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 22:13:20 +0000 (22:13 +0000)]
add some debug checking to get_pdecode_cr_out
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:55:57 +0000 (21:55 +0000)]
add crossreference to bug #603
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 21:44:48 +0000 (21:44 +0000)]
add more debug output to get_pdecode_cr_out
Cesar Strauss [Sat, 20 Feb 2021 21:12:03 +0000 (18:12 -0300)]
Actually forward the field width to field_slice()
This means that field extraction of multi-bit subfields, for field sizes
other than 64 bits, was buggy up to now.
Fortunately, there were no users of non-default field sizes so far.
Cesar Strauss [Sat, 20 Feb 2021 20:09:42 +0000 (17:09 -0300)]
Assemble the SV64 prefix from its subfields using SVP64PrefixFields
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:26 +0000 (20:49 +0000)]
start on CRs in SVP64 mode
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:49:00 +0000 (20:49 +0000)]
fix SVP64Asm Rc=1 assembly
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 20:47:48 +0000 (20:47 +0000)]
add black-box attribute to 4k SRAM cell
Cesar Strauss [Sat, 20 Feb 2021 18:39:41 +0000 (15:39 -0300)]
Fix more MSB0 issues in comments
Cesar Strauss [Sat, 20 Feb 2021 18:31:55 +0000 (15:31 -0300)]
Replace more hardcoded constants with symbolic field numbers
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 16:40:41 +0000 (16:40 +0000)]
increment CRs based on srcstep, see what happens
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:22:18 +0000 (15:22 +0000)]
add litex wishbone interconnect to 4x 4k SRAMs
also had to add one more of the massive DFF 512 byte SRAMs in order to cover
all the exception areas (0x900) without going into 4k SRAM area,
which litex demands to be on an aligned boundary
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:58:58 +0000 (14:58 +0000)]
add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer if enabled
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:39:14 +0000 (14:39 +0000)]
add option for QTY 4x 4k SRAM blocks (not added yet) to issuer_verilog
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 14:30:07 +0000 (14:30 +0000)]
add Wishbone-wrapped SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 13:55:47 +0000 (13:55 +0000)]
whoops set ROM to none by mistake
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:26:32 +0000 (12:26 +0000)]
whoops spelling error
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:23:04 +0000 (12:23 +0000)]
add (unused) code for writing out SVSTATE in TestIssuer
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:12:14 +0000 (12:12 +0000)]
correct arguments, set microwatt_mmu=True, pass in ROM correctly
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:10:11 +0000 (12:10 +0000)]
minor whitespace cleanup
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:03:35 +0000 (12:03 +0000)]
remove massive code-duplication, move simple "self.rom" to test_runner.py
the fu rom mmu unit test does seem to still work
Tobias Platen [Sat, 20 Feb 2021 11:53:41 +0000 (12:53 +0100)]
mmu testcase: set MMU SPRs
Tobias Platen [Sat, 20 Feb 2021 10:37:20 +0000 (11:37 +0100)]
add rom debugger
Tobias Platen [Sat, 20 Feb 2021 09:20:10 +0000 (10:20 +0100)]
add mmu rom testcase
Tobias Platen [Thu, 18 Feb 2021 19:45:48 +0000 (20:45 +0100)]
mmu: remove TestMemory
Luke Kenneth Casson Leighton [Wed, 17 Feb 2021 23:06:00 +0000 (23:06 +0000)]
declare blank classes SPEC and EXTRA2 to add MSB-to-LSB conversion
Cesar Strauss [Wed, 17 Feb 2021 22:53:01 +0000 (19:53 -0300)]
Use subfield bit selection to extract the RM SVP64 subfield
Cesar Strauss [Wed, 17 Feb 2021 22:30:29 +0000 (19:30 -0300)]
Replace MSB-i by symbolic subfield indices and selectors
Tobias Platen [Wed, 17 Feb 2021 17:30:54 +0000 (18:30 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 17 Feb 2021 17:30:20 +0000 (18:30 +0100)]
add wishbone signals to gtkwave output
Cesar Strauss [Wed, 17 Feb 2021 16:53:58 +0000 (13:53 -0300)]
Add the SVSTATE traces to GTKWave to allow debugging the SV loop
Cesar Strauss [Wed, 17 Feb 2021 16:50:09 +0000 (13:50 -0300)]
Initialize the core SVSTATE from the corresponding test case
Handle the case of initialization by integer, which is the default for all
test_issuer.py cases.
Cesar Strauss [Wed, 17 Feb 2021 15:36:22 +0000 (12:36 -0300)]
Revert "Setup SVSTATE, from the test settings, at the start"
This reverts commit
2bf9a3753b60fa1591b893bfb61de39c210a7d67.
Fix a breakage in test_issuer.py, while a proper solution is found.
Cesar Strauss [Wed, 17 Feb 2021 14:37:18 +0000 (11:37 -0300)]
Add a function to select bits from a signal into a subfield
Luke Kenneth Casson Leighton [Wed, 17 Feb 2021 12:31:06 +0000 (12:31 +0000)]
fix reg read/write in ISACaller, PowerDecoder2 handles is_vec now
Cesar Strauss [Wed, 17 Feb 2021 12:18:53 +0000 (09:18 -0300)]
Add a case for checking the EXTRA field and register augmenting
By carefully choosing unique v3.0b register numbers and Extra field
patterns, any mistake in encoding and decoding will likely be caught.
Cesar Strauss [Wed, 17 Feb 2021 12:02:19 +0000 (09:02 -0300)]
Add traces to debug SVP64 prefix decoding issues
Cesar Strauss [Wed, 17 Feb 2021 10:39:39 +0000 (07:39 -0300)]
Setup SVSTATE, from the test settings, at the start
Cesar Strauss [Tue, 16 Feb 2021 17:48:33 +0000 (14:48 -0300)]
Fix MSB0 issues for SVP64
Main changes are:
1) Convert indices from MSB0 to LSB0 when extracting fields
2) Convert indices from LSB0 to MSB0 when inserting fields
3) Reorder nMigen Records to start from the LSB
This was verified by inspecting the GTKWave output for
test_issuer_svp64.py, checking the instruction memory against a manually
assembled instruction, and checking that the decoded fields correspond to
the original instruction.
Tobias Platen [Tue, 16 Feb 2021 19:48:28 +0000 (20:48 +0100)]
mmureq handling
Tobias Platen [Tue, 16 Feb 2021 19:07:59 +0000 (20:07 +0100)]
dcache error handling
Tobias Platen [Tue, 16 Feb 2021 17:55:43 +0000 (18:55 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Luke Kenneth Casson Leighton [Tue, 16 Feb 2021 16:36:39 +0000 (16:36 +0000)]
ordering wrong on svstate in ISACaller
Luke Kenneth Casson Leighton [Tue, 16 Feb 2021 16:33:22 +0000 (16:33 +0000)]
adapt botchify so it can be used for 31- or 15- etc. etc.
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 14:06:39 +0000 (14:06 +0000)]
add indicator to PowerDecoder2 when no outputs are Vectorised
Cole Poirier [Mon, 15 Feb 2021 20:31:05 +0000 (12:31 -0800)]
remove file experiment/formal/proof_icache.py as it was reviewed and
determined to be not necessary at this point, if ever due to the
complexity of the icache, dcache, and mmu modules
Tobias Platen [Mon, 15 Feb 2021 17:07:23 +0000 (18:07 +0100)]
test case for MMU SPRs: PID and PRTBL
Cesar Strauss [Mon, 15 Feb 2021 17:06:12 +0000 (14:06 -0300)]
Simplify obtaining the PC from the register file
Tobias Platen [Mon, 15 Feb 2021 16:19:15 +0000 (17:19 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Cesar Strauss [Sun, 14 Feb 2021 22:49:02 +0000 (19:49 -0300)]
Show traces for the register numbers of the current instruction
Will make it easier to follow the vector loop, when it begins to increment
them.
Cesar Strauss [Sun, 14 Feb 2021 22:21:34 +0000 (19:21 -0300)]
Fix width of the "extra" input on the Extra decoder
The Extra field is nine bits long.
Cesar Strauss [Sun, 14 Feb 2021 21:47:02 +0000 (18:47 -0300)]
Fix conversion to MSB0
Correct formula is 31 - x.
Cesar Strauss [Sun, 14 Feb 2021 19:16:24 +0000 (16:16 -0300)]
Remove obsolete comment
Forgot to remove the TODO item when I implemented it.
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:25:56 +0000 (13:25 +0000)]
add comments to TestIssuer
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:12:38 +0000 (13:12 +0000)]
add srcstep onto Vectorised GPRs in PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:04:39 +0000 (13:04 +0000)]
add TestRunner comments
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 13:03:13 +0000 (13:03 +0000)]
add Regfiles comments
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 12:44:59 +0000 (12:44 +0000)]
add SVSTATE reading to TestIssuer
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 12:37:45 +0000 (12:37 +0000)]
add SVSTATE to CoreState
Luke Kenneth Casson Leighton [Sun, 14 Feb 2021 12:34:38 +0000 (12:34 +0000)]
add extra FSM explanatory comments to TestIssuer
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 22:53:22 +0000 (22:53 +0000)]
use function for getting instruction from 32/64 bit fetch
Cesar Strauss [Sat, 13 Feb 2021 21:40:27 +0000 (18:40 -0300)]
Fetch and decode the SVP64 prefix
After fetching the word at the PC, send it combinatorially to the SVP64
decoder. Pass the decoded prefix (if any) to PowerDecoder2. If it's not a
prefix, hand over the instruction to the decoder. Otherwise, initiate a
read from the next memory location. Adjust the next instruction address
accordingly.
Tobias Platen [Sat, 13 Feb 2021 20:23:28 +0000 (21:23 +0100)]
OP_TLBIE must in be instr_is_priv
Tobias Platen [Sat, 13 Feb 2021 20:13:50 +0000 (21:13 +0100)]
keep commits to under 80 chars
Cesar Strauss [Sat, 13 Feb 2021 19:55:39 +0000 (16:55 -0300)]
Check the PC value at the end of each instruction
Useful for checking that the PC really points to the next instruction,
after fetching a prefixed instruction.
Cesar Strauss [Sat, 13 Feb 2021 19:22:47 +0000 (16:22 -0300)]
Skip vector test case, and add a scalar case
Even if the prefix is a no-op, it will at least test the fetch unit.
Cesar Strauss [Sat, 13 Feb 2021 18:59:17 +0000 (15:59 -0300)]
Fix imports and whitespace
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 18:29:06 +0000 (18:29 +0000)]
update svp64 unit test comments
Tobias Platen [Sat, 13 Feb 2021 17:07:43 +0000 (18:07 +0100)]
forward microwatt mmu specific SPR: PID and PRTBL
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 12:27:08 +0000 (12:27 +0000)]
add SVP64 TestIssuer separate unit test
Luke Kenneth Casson Leighton [Sat, 13 Feb 2021 12:23:50 +0000 (12:23 +0000)]
split out TestRunner into separate module
Cesar Strauss [Sat, 13 Feb 2021 09:12:09 +0000 (06:12 -0300)]
Fix SVP64 translator to yield the unaltered instruction
Being a generator, it yields one item at a time, instead of appending to
a list.
Clean up the now unused return list, and simplify the iterator.
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:23:44 +0000 (15:23 +0000)]
add one SVP64 ALU test case to get started
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:23:05 +0000 (15:23 +0000)]
add SVSTATE to TestCase infrastructure for use in TestIssuer
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:07:09 +0000 (15:07 +0000)]
add skip of instruction if SVSTATE.VL=0 in ISACaller
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 15:02:43 +0000 (15:02 +0000)]
validate all registers to make sure no damage occurs in SVP64 ISACaller
Luke Kenneth Casson Leighton [Fri, 12 Feb 2021 14:41:48 +0000 (14:41 +0000)]
add srcstep and correct PC-advancing during Sub-PC looping in ISACaller