soc.git
3 years agosplit out SVEXTRA field selection/decoding into separate class SVP64ExtraSpec
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 12:55:21 +0000 (12:55 +0000)]
split out SVEXTRA field selection/decoding into separate class SVP64ExtraSpec
in PowerDecoder2

3 years agowhoops update PowerDecoder2 svp64 comments, reg sizes (7 bit)
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 12:46:38 +0000 (12:46 +0000)]
whoops update PowerDecoder2 svp64 comments, reg sizes (7 bit)

3 years agoadd SVP64 EXTRA decoding to RB, RC and RT (out) in PowerDecode2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 00:36:22 +0000 (00:36 +0000)]
add SVP64 EXTRA decoding to RB, RC and RT (out) in PowerDecode2
DecodeOut2 will have to wait because it is more complex

3 years agoadd first SVP64 7-bit register context decoder to PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 30 Jan 2021 00:17:20 +0000 (00:17 +0000)]
add first SVP64 7-bit register context decoder to PowerDecoder2

3 years agoadd SVP64RM record to PowerDecoder2
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 23:01:06 +0000 (23:01 +0000)]
add SVP64RM record to PowerDecoder2

3 years agoincrease register number sizes from 5 to 7
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 23:00:46 +0000 (23:00 +0000)]
increase register number sizes from 5 to 7

3 years agosyntax corrections, also size of maxvl was wrong
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:51:37 +0000 (22:51 +0000)]
syntax corrections, also size of maxvl was wrong

3 years agoadd SVP64 RM (Remap) Record
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:46:43 +0000 (22:46 +0000)]
add SVP64 RM (Remap) Record

3 years agoadjust SVP64RM class to output more PowerDecoder-friendly csv augmentation
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 22:39:44 +0000 (22:39 +0000)]
adjust SVP64RM class to output more PowerDecoder-friendly csv augmentation
add SVEXTRA power_enum
extend PowerDecoder fields (sv in/out regs)

3 years agoadjust how register copy/setup is done in PowerDecoder2
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 18:42:08 +0000 (18:42 +0000)]
adjust how register copy/setup is done in PowerDecoder2

3 years agoadd SV etype/ptype to power decoder
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 14:59:49 +0000 (14:59 +0000)]
add SV etype/ptype to power decoder

3 years agowhoops syntax error. submodule update
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 12:12:12 +0000 (12:12 +0000)]
whoops syntax error.  submodule update

3 years agostart adding svp64 enums
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:56:35 +0000 (11:56 +0000)]
start adding svp64 enums

3 years agouse new svp64-augmented csv reader in PowerDecoder
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:33:22 +0000 (11:33 +0000)]
use new svp64-augmented csv reader in PowerDecoder

3 years agowhoops missed out "+" on explicit license listing
Luke Kenneth Casson Leighton [Fri, 29 Jan 2021 11:19:14 +0000 (11:19 +0000)]
whoops missed out "+" on explicit license listing

3 years agoadd SVSTATE to StateRegs
Luke Kenneth Casson Leighton [Thu, 28 Jan 2021 16:07:29 +0000 (16:07 +0000)]
add SVSTATE to StateRegs
(also fix comments)

3 years agoadd SVState SPR Record, SVSTATERec
Luke Kenneth Casson Leighton [Thu, 28 Jan 2021 15:53:50 +0000 (15:53 +0000)]
add SVState SPR Record, SVSTATERec

3 years agoadd svp64 CR field identification for EXTRA2/3 decoding
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 18:38:34 +0000 (18:38 +0000)]
add svp64 CR field identification for EXTRA2/3 decoding

3 years agomove svp64 reg-decode function to more appropriate location
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 18:16:47 +0000 (18:16 +0000)]
move svp64 reg-decode function to more appropriate location
use it in SVP64RM get_svp64_csv to decode EXTRA bit-field positions

3 years agoprovide "merger" of SVP64 RM info into v3.0B CSV files
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:49:05 +0000 (12:49 +0000)]
provide "merger" of SVP64 RM info into v3.0B CSV files

3 years agouse SPR constants
Tobias Platen [Wed, 27 Jan 2021 19:45:37 +0000 (20:45 +0100)]
use SPR constants

3 years agomove SVP64RM CSV class to new module
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:38:35 +0000 (12:38 +0000)]
move SVP64RM CSV class to new module

3 years agowhitespace and shortening of SPR MMU redirection in Power Decoder
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:35:30 +0000 (12:35 +0000)]
whitespace and shortening of SPR MMU redirection in Power Decoder

3 years agoalso read LDST RM files
Luke Kenneth Casson Leighton [Wed, 27 Jan 2021 12:25:40 +0000 (12:25 +0000)]
also read LDST RM files

3 years ago[Bug 580] update comment above changed block
Tobias Platen [Tue, 26 Jan 2021 19:37:41 +0000 (20:37 +0100)]
[Bug 580] update comment above changed block

3 years ago[Bug 580] redirect MMU SPRs to the MMU
Tobias Platen [Tue, 26 Jan 2021 19:27:40 +0000 (20:27 +0100)]
[Bug 580] redirect MMU SPRs to the MMU

3 years agoextra comments in svp64
Luke Kenneth Casson Leighton [Mon, 25 Jan 2021 16:23:07 +0000 (16:23 +0000)]
extra comments in svp64

3 years agochanging svp64 asm syntax to use / instead of . as separators 24jan2021_ls180
Luke Kenneth Casson Leighton [Sun, 24 Jan 2021 11:35:43 +0000 (11:35 +0000)]
changing svp64 asm syntax to use / instead of . as separators

3 years agomove sanity-checks, add mode into svp64_rm
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 21:43:36 +0000 (21:43 +0000)]
move sanity-checks, add mode into svp64_rm

3 years agocleanup on aisle 3 - simplify sv_mode svp64
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 21:39:26 +0000 (21:39 +0000)]
cleanup on aisle 3 - simplify sv_mode  svp64

3 years agocheck src/dest mask exist if zeroing, svp64
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 21:30:30 +0000 (21:30 +0000)]
check src/dest mask exist if zeroing, svp64

3 years agoadd predicate-result svp64 decoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 20:58:03 +0000 (20:58 +0000)]
add predicate-result svp64 decoding

3 years agoadd svp64 saturation decoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 20:50:30 +0000 (20:50 +0000)]
add svp64 saturation decoding

3 years agostart decoding modes in svp64
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 20:44:58 +0000 (20:44 +0000)]
start decoding modes in svp64

3 years agoand now for something completely different...
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 19:19:47 +0000 (19:19 +0000)]
and now for something completely different...

3 years agoadd elwidth encoding svp64, add more debug-print
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 19:14:19 +0000 (19:14 +0000)]
add elwidth encoding svp64, add more debug-print

3 years agoadd svp64 subvl encoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 18:41:28 +0000 (18:41 +0000)]
add svp64 subvl encoding

3 years agoadd in svp64 predicate mask encoding
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 18:35:33 +0000 (18:35 +0000)]
add in svp64 predicate mask encoding

3 years agocapture CR 3 and 5 bit sv encodings
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 18:03:41 +0000 (18:03 +0000)]
capture CR 3 and 5 bit sv encodings

3 years agostart decoding EXTRA2/3
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 16:01:02 +0000 (16:01 +0000)]
start decoding EXTRA2/3

3 years agostart decoding sv EXTRAs and identifying them
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 15:38:17 +0000 (15:38 +0000)]
start decoding sv EXTRAs and identifying them

3 years agostart to read RM CSV files
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 15:02:59 +0000 (15:02 +0000)]
start to read RM CSV files

3 years agoadd beginnings of svp64 assembly translator
Luke Kenneth Casson Leighton [Sat, 23 Jan 2021 13:23:58 +0000 (13:23 +0000)]
add beginnings of svp64 assembly translator

3 years agoadd example on how to access regs list for cmp
Luke Kenneth Casson Leighton [Fri, 22 Jan 2021 20:04:31 +0000 (20:04 +0000)]
add example on how to access regs list for cmp

3 years agotest_issuer_mmu_data_path.py: test both ld and st instructions
Tobias Platen [Tue, 19 Jan 2021 18:54:45 +0000 (19:54 +0100)]
test_issuer_mmu_data_path.py: test both ld and st instructions

3 years agoconnect LDSTException to MMU and DCache
Tobias Platen [Tue, 19 Jan 2021 18:40:07 +0000 (19:40 +0100)]
connect LDSTException to MMU and DCache

3 years agoconnect wishbone bus to test memory
Tobias Platen [Tue, 19 Jan 2021 17:21:50 +0000 (18:21 +0100)]
connect wishbone bus to test memory

3 years agouncomment #FIXME in unit_test
Tobias Platen [Mon, 18 Jan 2021 19:51:59 +0000 (20:51 +0100)]
uncomment #FIXME in unit_test

3 years agofu/mmu/fsm.py: connect valid and load signals
Tobias Platen [Mon, 18 Jan 2021 17:25:13 +0000 (18:25 +0100)]
fu/mmu/fsm.py: connect valid and load signals

3 years agoadd test memory for simulation
Tobias Platen [Sun, 17 Jan 2021 16:48:26 +0000 (17:48 +0100)]
add test memory for simulation

3 years agocleanup test_issuer_mmu_data_path.py
Tobias Platen [Sun, 17 Jan 2021 15:59:22 +0000 (16:59 +0100)]
cleanup test_issuer_mmu_data_path.py

3 years agoclean up test case for tlbie and dcbz
Tobias Platen [Sat, 16 Jan 2021 17:31:48 +0000 (18:31 +0100)]
clean up test case for tlbie and dcbz

3 years agomove microwatt_mmu bool variable to pspec
Tobias Platen [Sat, 16 Jan 2021 16:43:46 +0000 (17:43 +0100)]
move microwatt_mmu bool variable to pspec

3 years agoadd new unittest: test_issuer_mmu_data_path.py
Tobias Platen [Sat, 16 Jan 2021 10:00:07 +0000 (11:00 +0100)]
add new unittest: test_issuer_mmu_data_path.py

3 years agocleanup test_non_production_core.py
Tobias Platen [Fri, 15 Jan 2021 18:16:57 +0000 (19:16 +0100)]
cleanup test_non_production_core.py

3 years agoadd microwatt_mmu boolean variable to core and compunits
Tobias Platen [Fri, 15 Jan 2021 18:05:36 +0000 (19:05 +0100)]
add microwatt_mmu boolean variable to core and compunits

3 years agotest_non_production_core.py: fix hanging test
Tobias Platen [Fri, 15 Jan 2021 17:56:18 +0000 (18:56 +0100)]
test_non_production_core.py: fix hanging test

3 years agotest_non_production_core.py: wire instruction decoder to core
Tobias Platen [Fri, 15 Jan 2021 16:50:16 +0000 (17:50 +0100)]
test_non_production_core.py: wire instruction decoder to core

3 years agoadd test case for mmu+NonProductionCore
Tobias Platen [Thu, 14 Jan 2021 20:06:55 +0000 (21:06 +0100)]
add test case for mmu+NonProductionCore

3 years agoadd microwatt mmu config option to compunits.py
Tobias Platen [Sun, 10 Jan 2021 13:05:03 +0000 (14:05 +0100)]
add microwatt mmu config option to compunits.py

3 years agofix broken testcase for simple core
Tobias Platen [Fri, 8 Jan 2021 20:11:06 +0000 (21:11 +0100)]
fix broken testcase for simple core

3 years agoset initial_sprs, cleanup mfspr testprog
Tobias Platen [Thu, 7 Jan 2021 17:25:48 +0000 (18:25 +0100)]
set initial_sprs, cleanup mfspr testprog

3 years agomfspr is RT, SPR
Tobias Platen [Thu, 7 Jan 2021 16:50:28 +0000 (17:50 +0100)]
mfspr is RT, SPR

3 years agofirst testcase for mmu: case_mfspr_after_invalid_load
Tobias Platen [Wed, 6 Jan 2021 18:49:36 +0000 (19:49 +0100)]
first testcase for mmu: case_mfspr_after_invalid_load

3 years agofu/mmu/fsm.py: mfspr!=mtspr
Tobias Platen [Wed, 6 Jan 2021 18:26:52 +0000 (19:26 +0100)]
fu/mmu/fsm.py: mfspr!=mtspr

3 years agotest_countzero.py: rename output files
Tobias Platen [Mon, 4 Jan 2021 17:58:31 +0000 (18:58 +0100)]
test_countzero.py: rename output files

3 years agoAdd zero CR test case and fix comments
Cesar Strauss [Fri, 1 Jan 2021 21:05:38 +0000 (18:05 -0300)]
Add zero CR test case and fix comments

3 years agoAdd test cases with rc=1
Cesar Strauss [Fri, 1 Jan 2021 20:58:07 +0000 (17:58 -0300)]
Add test cases with rc=1

Checks that the CR port produces results.

3 years agoMake all ports the same size, on the test ALU
Cesar Strauss [Fri, 1 Jan 2021 20:38:57 +0000 (17:38 -0300)]
Make all ports the same size, on the test ALU

The old regspec API can't cope with different port sizes.
The CR port is now changed from 3 to "width" bits (16).
The problem was that cr.ok went into the fourth bit, messing with
the results.

3 years agoAdd CR output port to test cases
Cesar Strauss [Fri, 1 Jan 2021 18:34:24 +0000 (15:34 -0300)]
Add CR output port to test cases

Test cases can now set rc=1, and expect results in the CR port.
wrmask and dest_delay arrays have incremented their length accordingly.

3 years agoAdd CR to the output data port
Cesar Strauss [Fri, 1 Jan 2021 17:46:35 +0000 (14:46 -0300)]
Add CR to the output data port

3 years agoMake output write enables independent of valid_o
Cesar Strauss [Fri, 1 Jan 2021 15:06:48 +0000 (12:06 -0300)]
Make output write enables independent of valid_o

Just combinatiorally decode the operation.
This is because MultiCompUnit depends on *_ok being kept valid.

3 years agoMove NOP test case earlier
Cesar Strauss [Fri, 1 Jan 2021 14:11:24 +0000 (11:11 -0300)]
Move NOP test case earlier

Better way to see alu_o_ok being disabled during the instruction.

3 years agoDisable data value output on NOP
Cesar Strauss [Fri, 1 Jan 2021 12:59:49 +0000 (09:59 -0300)]
Disable data value output on NOP

3 years agoAdd condition register (CR) output
Cesar Strauss [Fri, 1 Jan 2021 12:54:45 +0000 (09:54 -0300)]
Add condition register (CR) output

3 years agoImplement and test NOP in the test ALU
Cesar Strauss [Thu, 31 Dec 2020 21:41:18 +0000 (18:41 -0300)]
Implement and test NOP in the test ALU

Change the output port from Signal to Data, to allow for the output to be
masked-out.

Specify a masked-out output in the NOP test case.

3 years agoDon't use OP_NOP for zero-delay subtraction
Cesar Strauss [Thu, 31 Dec 2020 20:43:34 +0000 (17:43 -0300)]
Don't use OP_NOP for zero-delay subtraction

We are going to implement an actual NOP

3 years agoTest first input port being masked out
Cesar Strauss [Thu, 31 Dec 2020 20:31:41 +0000 (17:31 -0300)]
Test first input port being masked out

3 years agoSign extend the second input port
Cesar Strauss [Thu, 31 Dec 2020 20:28:05 +0000 (17:28 -0300)]
Sign extend the second input port

3 years agoTest masked-out second input port
Cesar Strauss [Thu, 31 Dec 2020 20:06:56 +0000 (17:06 -0300)]
Test masked-out second input port

Sign extend uses only the first port.

3 years agoAdd sign extend to the Test ALU
Cesar Strauss [Thu, 31 Dec 2020 19:51:03 +0000 (16:51 -0300)]
Add sign extend to the Test ALU

3 years agoShow rdmaskn and wrmask in GTKWave
Cesar Strauss [Thu, 31 Dec 2020 13:36:58 +0000 (10:36 -0300)]
Show rdmaskn and wrmask in GTKWave

3 years agoUse the increment operator
Cesar Strauss [Thu, 31 Dec 2020 13:08:41 +0000 (10:08 -0300)]
Use the increment operator

3 years agoAdd support for masked write operations
Cesar Strauss [Thu, 31 Dec 2020 13:04:05 +0000 (10:04 -0300)]
Add support for masked write operations

Note that the test ALU currently does not have any masked writes.

3 years agoClarify reason for holding rdmaskn valid during the entire cycle
Cesar Strauss [Thu, 31 Dec 2020 12:20:13 +0000 (12:20 +0000)]
Clarify reason for holding rdmaskn valid during the entire cycle

3 years agoRemove previous version of the CompUnit parallel unit test
Cesar Strauss [Thu, 31 Dec 2020 10:42:27 +0000 (10:42 +0000)]
Remove previous version of the CompUnit parallel unit test

It was too detailed, modeling properties which are better checked by
formal verification.

Other than that, the new version has reached feature parity, so the old
code can finally be removed.

3 years agoOnly hold the decoder signals for one cycle, along with issue_i
Cesar Strauss [Thu, 31 Dec 2020 10:22:04 +0000 (10:22 +0000)]
Only hold the decoder signals for one cycle, along with issue_i

The exception is rdmaskn, which is not latched, and must be held valid
for the entire instrucion cycle.

3 years agoTest the rdmaskn control signal
Cesar Strauss [Wed, 30 Dec 2020 21:00:38 +0000 (21:00 +0000)]
Test the rdmaskn control signal

The operation issuer now can drive the rdmaskn signals, and check
that the operand fetch on any masked ports is supressed.

3 years agoRemove left-over comments.
Cesar Strauss [Tue, 29 Dec 2020 11:26:29 +0000 (11:26 +0000)]
Remove left-over comments.

The debug signals were removed in a previous commit, but the comment
lines remained.

3 years agoadd CR1 to power_enums
Luke Kenneth Casson Leighton [Mon, 28 Dec 2020 20:30:34 +0000 (20:30 +0000)]
add CR1 to power_enums

3 years agoAdd support for CXXSim simulation
Cesar Strauss [Sun, 20 Dec 2020 14:18:34 +0000 (11:18 -0300)]
Add support for CXXSim simulation

3 years agoIgnore formal verification output in the source directory
Cesar Strauss [Sun, 13 Dec 2020 18:16:29 +0000 (15:16 -0300)]
Ignore formal verification output in the source directory

This is similarly done in other sister directories.

3 years agoAllow more test cases to be run with CXXSim
Cesar Strauss [Sun, 13 Dec 2020 18:03:59 +0000 (15:03 -0300)]
Allow more test cases to be run with CXXSim

3 years agoskip madd, not implemented
Luke Kenneth Casson Leighton [Sat, 12 Dec 2020 16:37:49 +0000 (16:37 +0000)]
skip madd, not implemented

3 years agoupdate submodules
Luke Kenneth Casson Leighton [Wed, 9 Dec 2020 18:13:28 +0000 (18:13 +0000)]
update submodules

3 years agoupdate submodules
Luke Kenneth Casson Leighton [Wed, 9 Dec 2020 18:10:48 +0000 (18:10 +0000)]
update submodules

3 years agoDisplay the instruction type as a vector on cxxsim
Cesar Strauss [Mon, 7 Dec 2020 21:44:40 +0000 (18:44 -0300)]
Display the instruction type as a vector on cxxsim

It doesn't support enums traces yet.

3 years agoattempt to split into two separate GPIO banks due to a coriolis2 compile error
Luke Kenneth Casson Leighton [Sun, 6 Dec 2020 19:35:57 +0000 (19:35 +0000)]
attempt to split into two separate GPIO banks due to a coriolis2 compile error

3 years agoWhitespace
Cesar Strauss [Sun, 6 Dec 2020 12:31:31 +0000 (09:31 -0300)]
Whitespace

3 years agoUpdate GTKWave documents to work with latest cxxsim
Cesar Strauss [Sun, 6 Dec 2020 11:34:35 +0000 (08:34 -0300)]
Update GTKWave documents to work with latest cxxsim

* Hierarchy begins at "top", just like pysim
* Avoid intermediate signals, that work differently on both
* Use the new "submodule" style in write_gtkw