arch-power: Fix shift instructions

Now that 64-bit registers are being used, the instructions
must use only the lower word of the operand to be shifted.
This fixes the following instructions.
  * Shift Left Word (slw[.])
  * Shift Right Word (srw[.])
  * Shift Right Algebraic Word (sraw[.])
  * Shift Right Algebraic Word Immediate (srawi[.])

Change-Id: Ibc3124b9e3a8660b0ff9d0178218e34bcc028310
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor shift instructions

This changes the format for integer shift instructions
such that the computation of the carry bit is implicitly
handled rather than including it in the definition of an
instruction.

Change-Id: Ib916597287efd51b2c9e8781209a8019f2fc38e8
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add bit permute instructions

This adds the following instructions.
  * Bit Permute Doubleword (bpermd)

Change-Id: Iab3cc6729b9d59c95e29b4f1d3e2c0eb48fde917
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add parity instructions

This adds the following instructions.
  * Parity Word (prtyw)
  * Parity Doubleword (prtyd)

Change-Id: Ic102d722f1bc8cea4921ddbf9febfa0e7c0f892e
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add population count instructions

This adds the following instructions.
  * Population Count Bytes (popcntb)
  * Population Count Words (popcntw)
  * Population Count Doubleword (popcntd)

Change-Id: Id15188482b45552735c1d960418d5d6ba1f2ede8
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add zero count instructions

This introduces new helpers for finding the count of
leading and trailing zero bits in a given value and adds
the following instructions.
  * Count Trailing Zeros Word (cnttzw[.])
  * Count Leading Zeros Doubleword (cntlzd[.])
  * Count Trailing Zeros Doubleword (cnttzd[.])

Change-Id: I69dad34bc2cffb2ac70ecd3dba7301fa1cdcb340
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add sign-extend instructions

This adds the following instructions.
  * Extend Sign Word (extsw[.])

Change-Id: Ia15fc69de665399f1c8d52ca00d2f7670d553b48
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix disassembly for logical instructions

This fixes disassembly generated for integer logical
instructions based on the type of operands and special
use cases for which the Power ISA provides extended
mnemonics.

Change-Id: I6b67569ef413b0b542e35082ca360c9b4262fc5b
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix logical instructions

Now that 64-bit registers are being used, the instructions
performing comparisons must use the entire 64 bits of the
register operands. Also, most of these instructions need
to determine the nature of the result if the Rc bit is set.
This fixes the following instructions.
  * AND (and[.])
  * OR (or[.])
  * XOR (xor[.])
  * NAND (nand[.])
  * NOR (nor[.])
  * Equivalent (eqv[.])
  * AND with Complement (andc[.])
  * OR with Complement (orc[.])
  * Extend Sign Byte (extsb[.])
  * Extend Sign Halfword (extsh[.])
  * Count Leading Zeros Word (cntlzw[.])
  * Compare Bytes (cmpb)

Change-Id: Ifecb0779fa6e2062d382f9abf8b2cfaf7cea3c96
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor logical instructions

This changes the base class for integer logical instructions
and adds a new class that is used to distinguish between
instructions using different operand types, i.e. register or
immediate. The formats have also been updated to make use of
the new base classes.

Change-Id: Id780cdb16405b01e82dcd22dc6e885ee15b716b2
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add character compare instructions

This adds the following instructions.
  * Compare Ranged Byte (cmprb)
  * Compare Equal Byte (cmpeqb)

Change-Id: I12a9135bf302acd741abe27cb557e8e8bba82edc
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix disassembly for compare instructions

This fixes disassembly generated for integer compare
instructions based on the type of operands, the type of
comparison to be made and the special use cases for which
the Power ISA provides extended mnemonics.

Change-Id: Ia052bef9589cc3ed290400390028398be28c8eff
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix compare instructions

Now that 64-bit registers are being used, instead of always
performing a 32-bit comparison, these instructions must use
the L field to determine the type of comparison to be made.
The comparison can either be 32-bit or 64-bit. This fixes
the following instructions.
  * Compare (cmp)
  * Compare Logical (cmpl)
  * Compare Immediate (cmpi)
  * Compare Logical Immediate (cmpli)

Change-Id: Ia7655ffa463214c24e094e01d4188decf6486904
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor compare instructions

This changes the base class for integer compare instructions
and adds two new classes that are used to distinguish between
instructions using different operand types, i.e. register or
immediate, and comparison types, i.e. signed or unsigned. The
formats have also been updated to make use of the new base
classes.

Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add fields for D and X form instructions

This adds the L field for D and X form instructions that
specifies if a compare instruction should perform 32-bit
or 64-bit comparison of its operands.

Change-Id: I72413a507c93096b1573836197837227c1c1e521
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add doubleword modulo instructions

This adds the following instructions.
  * Modulo Signed Doubleword (modsd)
  * Modulo Unsigned Doubleword (modud)

Change-Id: Ic7bcb85869ccedf5c95aadfe925c85b3b1155031
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add word modulo instructions

This adds the following instructions.
  * Modulo Signed Word (modsw)
  * Modulo Unsigned Word (moduw)

Change-Id: Id84ff46d0114ab859bd8616d3dcf22111cf3bda2
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add doubleword divide-extended instructions

This introduces 128-bit division helpers for adds the
following instructions.
  * Divide Doubleword Extended (divde[o][.])
  * Divide Doubleword Extended Unsigned (divdeu[o][.])

Change-Id: I3591d91f22df2dce74fed5147d5de2ce82a83642
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add doubleword divide instructions

This adds the following instructions.
  * Divide Doubleword (divd[o][.])
  * Divide Doubleword Unsigned (divdu[o][.])

Change-Id: Id233a860fcb4b47c8397163a500c783f37be5dd4
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add word divide-extended instructions

This adds the following instructions.
  * Divide Word Extended (divwe[o][.])
  * Divide Word Extended Unsigned (divweu[o][.])

Change-Id: Ie399269938c8e120ece667ce3fc9c6fe1d74faca
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add doubleword multiply-add instructions

This introduces 128-bit addition helpers and adds the
following instructions.
  * Multiply-Add Low Doubleword (maddld)
  * Multiply-Add High Doubleword (maddhd)
  * Multiply-Add High Doubleword Unsigned (maddhdu)

Change-Id: I04e6ea5fb4978b341a6e648424de2930ad41f449
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add fields for VA form instructions

This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.

Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add doubleword multiply instructions

This introduces 128-bit multiplication helpers and adds
the following instructions.
  * Multiply Low Doubleword (mulld[o][.])
  * Multiply High Doubleword (mulhd[.])
  * Multiply High Doubleword Unsigned (mulhdu[.])

Change-Id: Id579c95468ffe5fe7b5164579ec1dfb18f0b3ab3
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add PC-relative arithmetic instructions

This adds the following instructions.
  * Add PC Immediate Shifted (addpcis)

Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add fields for DX form instructions

This introduces the extended opcode field for DS form
instructions and the fields d0, d1 and d2 which are
concatenated for specifying a signed integer immediate
operand.

Change-Id: Id60e85d79f9157d680f813bf90ab6e1e064253a9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix disassembly for arithmetic instructions

This fixes disassembly generated for integer add and subtract
arithmetic instructions based on the type of operands and the
special use cases for which the Power ISA provides extended
mnemonics.

Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix arithmetic instructions

The latest Power ISA introduces two new bits that record
carry and overflow out of bit 31 of the result, namely
CA32 and OV32 respectively, thereby changing the behaviour
of the add and subtract instructions that set them. Also,
now that 64-bit registers are being used, the nature of
the result, i.e. less than, greater than or equal to zero,
must be set by a 64-bit signed comparison of the result
to zero. This fixes the following instructions.
  * Add Immediate (addi)
  * Add Immediate Shifted (addis)
  * Add (add[o][.])
  * Subtract From (subf[o][.])
  * Add Immediate Carrying (addic)
  * Add Immediate Carrying and Record (addic.)
  * Subtract From Immediate Carrying (subfic)
  * Add Carrying (addc[o][.])
  * Subtract From Carrying (subfc[o][.])
  * Add Extended (adde[o][.])
  * Subtract From Extended (subfe[o][.])
  * Add to Zero Extended (addze[o][.])
  * Subtract From Zero Extended (subfze[o][.])
  * Negate (neg[o][.])
  * Multiply Low Immediate (mulli)
  * Multiply Low Word (mullw[o][.])
  * Multiply High Word (mulhw[.])
  * Multiply High Word Unsigned (mulhwu[.])
  * Divide Word (divw[o][.])
  * Divide Word Unsigned (divwu[o][.])

Change-Id: I8c79f1dca8b19010ed7b734d7ec9bb598df428c3
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor arithmetic instructions

This changes the base classes for integer arithmetic
instructions and introduces two new classes that are used
to distinguish between instructions using register and
immediate operands.

Decoding has also been consolidated using formats that can
generate code after determining if an instruction records
carry and overflow and also if it records the nature of the
result, i.e. lesser than, greater than or equal to zero.
However, for multiply and divide instructions, the code to
determine if an overflow has occurred has been moved to the
instruction definition itself. The formats have also been
updated to make use of the new base classes.

Change-Id: I23d70ac4bad4d25d876308db0b3564c092bf574c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add atomic load-store instructions

This adds the following instructions.
  * Load Byte And Reserve Indexed (lbarx)
  * Load Halfword And Reserve Indexed (lharx)
  * Load Doubleword And Reserve Indexed (ldarx)
  * Store Byte Conditional Indexed (stbcx.)
  * Store Halfword Conditional Indexed (sthcx.)
  * Store Doubleword Conditional Indexed (stdcx.)

Change-Id: Ie85d57e7e111f06dd0f17f9f4d0953be44ef5fb8
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add byte-reversed load-store instructions

This adds the following instructions.
  * Load Halfword Byte-Reverse Indexed (lhbrx)
  * Load Word Byte-Reverse Indexed (lwbrx)
  * Load Doubleword Byte-Reverse Indexed (ldbrx)
  * Store Halfword Byte-Reverse Indexed (sthbrx)
  * Store Word Byte-Reverse Indexed (stwbrx)
  * Store Doubleword Byte-Reverse Indexed (stdbrx)

Change-Id: Id7aae44c370d6376410ab8c82839b908ea6ca196
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add doubleword load-store instructions

This introduces new formats for DS form instructions and
adds the following instructions.
  * Load Doubleword (ld)
  * Load Doubleword Indexed (ldx)
  * Load Doubleword with Update (ldu)
  * Load Doubleword with Update Indexed (ldux)
  * Store Doubleword (std)
  * Store Doubleword Indexed (stdx)
  * Store Doubleword with Update (stdu)
  * Store Doubleword with Update Indexed (stdux)

Change-Id: I2a88364e82a11685e081f57be5fd5afd44335668
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix disassembly for load-store instructions

This fixes disassembly generated for load-store instructions
based on how the base classess that are used to distinguish
between the types of operands used by these instructions.

Change-Id: I5a0f8644cdc6fec934475536861ad342c0a1fb4c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix load-store instructions

Now that 64-bit registers and operands are being used, the
instructions for words must read or write just one word at
a time. This fixes the following instructions.
  * Load Word and Zero (lwz)
  * Load Word and Zero Indexed (lwzx)
  * Load Word and Zero with Update (lwzu)
  * Load Word and Zero with Update Indexed (lwzux)
  * Load Word And Reserve Indexed (lwarx)
  * Store Word (stw)
  * Store Word Indexed (stwx)
  * Store Word with Update (stwu)
  * Store Word with Update Indexed (stwux)
  * Store Word Conditional Indexed (stwcx.)

This also fixes decoding of load-store update instructions
for some special scenarios when RA is zero or RA and RT
are the same. In such cases, the instruction is considered
invalid.

Change-Id: I6787d3614ba8f1b1cbf30a49f85ef422324d7c21
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor load-store instructions

This changes the base classes for load-store instructions
and introduces two new classes for DS form instructions
which use a shifted signed immediate field as the offset
from the base address and for X form instructions which
use registers for both the offset and the base address.
The formats have also been updated to make use of the new
base classes.

Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add fields for DS form instructions

This introduces the DS field used by DS form instructions
which specifies a signed integer immediate operand.

Change-Id: I0e7a77e7a63fce4e50b7941850c277f556e65724
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix precedence of register operands

When RS and RA are both used as operands by an instruction,
RS takes precedence over RA. In such cases, either both the
register operands are used as sources or RS is a source and
RA is a destination.

This changes the order by giving RS the highest precedence
and will be useful for proper disassembly generation.

Change-Id: If351a03a814653f2f371afa936ec7a5cd4377b3a
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add TAR and associated instructions

This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it.
  * Move To Target Address Register (mttar)
  * Move From Target Address Register (mftar)
  * Branch Conditional to Branch Target Address Register (bctar[l])

Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix disassembly for branch instructions

This fixes disassembly generated for branch instructions
based on the AA and LK bits which determine how the target
address is calculated and whether a return address needs
to be set implicitly or not.

Change-Id: I1acba72c360a1fcb4691de17fbae1a012a752dbe
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix branch conditional instructions

Among the register-based conditional branch instructions,
the ones using CTR should not decrement CTR when the bit
corresponding to this action is set in the BO field of
the instruction. In this case, the instruction should be
considered invalid. This fixes the following instructions.
  * Branch Conditional to Count Register (bcctr[l])

Change-Id: Ib2dbf2bc36fced580b4b7f7b76783f68361f6bbf
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor branch instructions

This changes the base classes for branch instructions and
switches to two high-level classes for unconditional and
conditional branches. The conditional branches are further
classified based on whether they use an immediate field or
a register for determining the target address.

Decoding has also been consolidated using formats that can
generate code after determining if an instruction branches
to an absolute address or a PC-relative address, or if it
implicitly sets the return address by looking at the AA and
LK bits.

Change-Id: I5fa7db7b6693586b4ea3c71e5cad8a60753de29c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Fix extended opcode based decoding

When multiple instructions share the same primary opcode,
they are distinguished by the decoder by looking at the
extended opcode. However, the length and position of the
extended opcode field can vary based on instruction form.

This ensures that the correct extended opcode fields are
used for decoding such instructions.

Change-Id: I8207568ac975587377abba8a9b221ca3097b8488
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Add and rename some opcode fields

This introduces separate extended opcode (XO) fields for DS,
X, XFL, XFX, XL and XO form instructions and renames the
primary opcode field to PO based on the convention used in
the Power ISA manual.

Change-Id: I82598efe74c02960f38fe4ed5e22599340f7e15c
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor instruction decoding

This reorders the decoding logic based on the category of
instructions. The ordering scheme used here is roughly in
line with the Power ISA manual as shown below.
  * Branch facility instructions
      * Branch instructions
      * Condition Register instructions
      * System Call instructions
  * Fixed-point facility instructions
      * Load instructions
      * Store instructions
      * Arithmetic instructions
      * Compare instructions
      * Logical instructions
      * Rotate and Shift instructions
      * Move To/From System Register instructions
  * Floating-point facility instructions
      * Load instructions
      * Store instructions
      * Arithmetic instructions
      * Move instructions
      * Rounding and Conversion instructions
      * Compare instructions
      * Status and Control Register instructions

Change-Id: Ia2d457967bfebb7b20163b56db1cbbe03ac17ceb
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Refactor special purpose registers

This converts the definitions of all the currently defined
Special Purpose Registers (SPRs) to miscellaneous registers
which allows us to print the corresponding SPR name in the
debug logs rather than an ambiguous register number making
things much easier to correlate.

Change-Id: I03f10e3a44a8437beec453dfae2207d71ce43c1e
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

arch-power: Use 64-bit registers and operands

This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with the newer versions of the Power ISA and
enables usage in both 32-bit and 64-bit execution modes.
In 32-bit mode, the use of upper word is dependent on the
instruction being executed and in some cases this may be
undefined.

Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

base: Add enum to_number tests

Add a test to convert a string containing a number into enums.

One of the tests has been disabled to highlight an error-prone
situation where a number that is not a valid enum manages to
be converted to an enum.

Change-Id: I7967c62feea335f3ffda40d8bf0334c20b53ee6c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41334
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Work around a scons bug when calling TryCompile.

When calling TryCompile with an empty string for the source, useful
when just testing a build flag, some versions of SCons will apparently
create some sort of equivalence between Value('') and Value(0). That
shows itself when creating config file headers, where Value(0) is
switched with Value(''), and the header defines a macro with which
expands to nothing rather than a macro which expands to 0. Later uses
of the macro of the form:

 #if CONFIG_VARIABLE

fail because CONFIG_VARIABLE expands to nothing. If it expanded to 0
like it's supposed to, then the guarded block of code would be excluded
correctly.

Change-Id: Ie324ec5f8dd307c65745b9326a11230e10caa0bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41213
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>

arch-x86: Use popCount from bitfields.hh.

Use popCount from bitfields.hh rather than call __builtin_popcountl
directly. That will ensure the instruction works whether or not that
builtin is available.

Change-Id: I947b35bb832b768936b489a58ee324adb8a90b5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41354
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Stop including unnecessary FP headers.

Nothing is used from them. They're probably there as copy/paste from
other ISAs, or old code that's been replaced. This also gets rid of some
 #if guarded includes which is a nice cleanup.

Change-Id: Icd84300fb7531ec203ce4acbdae1d311e56cc873
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41353
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: intToTick helper

Change-Id: I76635228223e9a83eef94a25d166d091315a5e96
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41156
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: add wakeup_port statement

While the wakeUpBuffers/wakeUpAllBuffers check all message buffers,
wakeup_port wakes up only the messages stalled on the specified port
and address. Usage is the same as the stall_and_wait statement, e.g.:

wakeup_port(reqInPort, addr);

Change-Id: I57dc77d574c0016ca55786ce16a73061a1d37f2e
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: add andMask to WriteMask

Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41154
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: more readable Ruby dot topology

Controllers may have the same name under different parents, thus
the controller full path is used as label. To avoid long and redundant
labels, common prefixes and suffixes are removed from the path.

Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41093
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Fix sign extension for branches with multiplied offset

Certain branch instructions specify that the result of (simm16 * 4)
gets sign-extended before being added to the PC.

Previously, that result was being sign extended as if it was still a
16-bit number. This patch fixes that by having the result be sign
extended as an 18-bit number.

Change-Id: Id4d430f8daa71ca7910b570e7e39790626f1decf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41053
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Simplify kvm architecture compatibility check.

The original implementation had a function we'd call back into later
which checked if a given ISA has KVM support on the current host.
Instead, this change reverse that and statically figures out which
single target ISA could possibly run under KVM on this host. Then later,
we can just check if the ISA we're trying to build is that one.

Change-Id: I3e7e06180983dfcc4611181718eb5d6210844d36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40870
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Merge redundant checks for the socket library.

scons can accept more than one library at a time, so lets check for both
at once instead of writing out almost the same check twice.

Change-Id: I82f9bdf59a349e28ca75a615d711051256ec73a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40869
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Simplify the check for protoc.

Collapse nesting, and constrain the try/except to only the line in that
section which might actually be expected to throw an exception when
things are working normally.

This makes the code easier to read, and won't absorb and discard
exceptions which are thrown for unexpected reasons.

Change-Id: Id3ac417ab5545bef35ed8a87d05211c8ef2f5a50
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40867
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Create a Configure checker for pkg-config.

This will check if a pkg-config package exists at all, and then if it
does will attempt to use the supplied pkg-config arguments and
ParseConfig to set up the environment as needed.

Change-Id: I1495e5370b60dcebb1c9ce38517e84d727abc2fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40866
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Simplify the check for hdf5 support.

Collapse the check_hdf5 to the only place it was called, to set a simple
flag variable. Pull the invariant have_pkg_config check out of
check_hdf5_pkg, since if we don't have pkg-config there's no reason to
even try to use to set up hdf5. Turn the one-off, non-standard "Warning"
print into an actual warning().

Change-Id: I04793ae862aeaf1605467d205837b9dd744f93cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40865
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Simplify backtrace implementation detection.

There are really only two options current, glibc or none. If there's a
working implementation there's no real reason to select none, and if
there isn't there's no other option but to select none.

Instead of building up a list, having a default, and making what option
on the list is selected configurable, boil it down to either using glibc
if that implementation is detected, or warning and using none. Also
merge the "normal" and *BSD versions of the checks to reduce redundancy.

The complexity can be added back in if/when there are other
implementations to choose from.

Change-Id: I27c77996a00018302f4daea40924cf059d5a4323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40864
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Simplify check for have_posix_clock.

The "library" argument can actually be a list, in which case each
element of the list is checked, one after the other. Use that rather
than calling the CheckLibWithHeader method multiple times and manually
oring the results.

Change-Id: I5c774be15eaa9a7e52ec3ee5a1bbcc5ef1fa0f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40863
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Move a displaced have_posix_clock check back where it goes.

This check had been separated from the code handling have_posix_clock by
some intervening code doing something else. Bring the check back
alongside the code setting that variable.

Change-Id: I6acb54fddbb5c41d6c38d4b93e649835a4775fa0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40862
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Use conf to determine if some flags are supported.

Use conf rather than checking for particular combinations of OS and/or
compiler versions. This *should* be just as correct, and not require
keeping track of what versions of the tools particular flags were added.

Change-Id: Icaa4c273fe89801e2808e6a814ce476700fd6956
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40861
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: In Check(Cxx|Link)Flag, only install the flag if it exists.

These functions where correctly returning whether a flag had existed,
and also correctly not installing it if asked not to. Unfortunately if
they *were* asked to install the flag, they ignored whether or not it
had actually existed to begin with.

Change-Id: I2dca0e1a0ddbc182576d48237aeea5452a02c51b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41159
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: fix Sequencer latency reporting

Most protocols won't set initialRequestTime, forwardRequestTime, and
firstResponseTime, thus leading to calculated latency being always 0.

Change-Id: Id2c73314a964bf6efb262d40b3df515373023b84
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41114
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: fix functional reads in abstract ctrl

When calling functionalMemoryRead we need to check the mem req. queue
first as it may have write data not yet forwarded to the memory port.

Change-Id: Id37aa0837a3462d92ae9ac3b45ca756b2c4f7d97
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41153
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: fixes for masked writes

This adds DataBlock::setData(PacketPtr) to update the block with
packet data. The method uses the packet's writeData to copy the
correct bytes if the request is a masked write.

Change-Id: I9e5f70fed29edcf55fef94a4b145aa838dc60eac
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: warns on masked functional writes

It's not expected to issue masked functional writes or to receive
functional writes to an address with a pending masked write.

Change-Id: Ibc8ba5f642ff72f897e3a50011c0da6d3000b741
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41133
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix CPTR_EL2 writes

* If E2H==1, CPTR_EL2.ZEN bits are not RES0.
* If E2H==1, CPTR_EL2.FPEN bits are not RES0.

Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39702
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Initialize pendingWrites stat of NVMStats

The initialization for this stat was mistakenly removed here
https://gem5-review.googlesource.com/c/public/gem5/+/39276

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I27b6ddf6d6b925c9787acb07552a8d5acb081c22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41073
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Pull Configure() to earlier in SConstruct so we can use it more.

This mechanism lets us check if headers are available, flags are
supported, etc. We should use that more often, rather than checking for
specific versions of tools where problematic new warnings were added, etc.

Change-Id: I5b1a6499147f27cc8944fcb8c61eb69e9fa8fb7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40860
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix copyright of base/stats/SConscript

The original copyright was accidentally removed by
e59557af500d1633b1f41b023d6c072acaf145a0.

Change-Id: Ib3b7a34ea889fbd9a6f2a8e21a6bb24432939da9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40755
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Extract the gem5 specific Configure call to its own file.

This modularizes that fairly generic code and pulls it out of the main
SConstruct file.

Change-Id: I5f5edc866af43753b4e0a9cc63774ded0fffe06b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40858
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Trim down a check for mac OS and arch setting flags.

This check used uname to determine if scons was running on macos, and
then a fairly elaborate check to see if the version was above 9, and if
the hardware supported 64 bit. I think at this point it's safe to assume
both that we're at least at macos 10 which is 19 years old, and that Mac
hardware supports 64 bit.

Change-Id: Ice66df2530bbcc929d3a37e7679634b75ba7b860
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40857
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Remove "TIMEOUT" variable and checks.

This was used when regression tests were run from scons. Since that
hasn't been done for a while, these checks and this setting have no
purpose and can be removed.

Change-Id: Ibe383944f1427571061fd25ed6e97d9acfbbc7f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40856
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Update the Check(Cxx|Link)Flag checks to set their vars.

This avoids boilerplate where we check to see if flag X is supported,
and if so then set flag X. Since there are shared and static versions of
the linker flags but we only explicitly check the static ones, this
change also adds a parameter to CheckLinkFlag to set both flavors. This
defaults to true since I assume most of the time linking flags will
apply to both.

Change-Id: I983222169e9835aeb98570362f7004e2ef0240d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40855
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Remove partial linking.

This feature didn't actually provide any benefit in the end, and
increased build directory size and scons complexity.

Change-Id: Ia5aa16a8dd008599645076cea8131799f6086e0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40795
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Delete the empty, default off "nocpu".

This very nearly empty CPU directory does nothing except define a CPU at
the scons level which is off by default. It seems safe to delete it.

Change-Id: I5bd3a52062bbc67fb1ee7d350519cd85a3f8fdb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40871
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

dev-arm: Add VRAM to VExpress_GEM5_Base

Change-Id: Ibd3ae59730c6d00a6bd8b129f973b79a565f66e4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40973
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add support for debug info compression.

If supported this will compress the debug information in object files,
libraries, and binaries. This decreases the size of the build/ARM
directory from 11GB to 7.2GB.

Because the benefit of this mechanism depends on the performance and
capacity of the build machine's storage, it can be disabled with the
--no-compress-debug scons flag. For instance if your storage is very
fast, writing out a larger binary may take less time than compressing
that same number of bytes, plus the time to write out the smaller
file.

This feature seems to make our presubmit test machine run out of memory
when trying to build gem5, and so is disabled in the testing scripts.

Change-Id: I71919062d23742b7658918b0fa9c4d91d0521fbf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40715
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove units from stats description

A recent change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump; the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units

Change-Id: Ib63ea44e757f755f761b20b40e045bc37c90baff
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40735
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>

arch-riscv: Fixed the style of stats variable names in TlbStats

The variable names should be of camel case style.

Change-Id: I397c9f165a53ecc120ec57f7214c90a65e12407e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40695
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

dev,dev-arm: Remove units from stats description

A recent change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump; the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units in the descriptions
are kept until unit prefixes are supported.

Change-Id: I199afbf29fee13b08eeb323c4cb56c8a974dbe94
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40675
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>

mem: Remove units from stats description

The change https://gem5-review.googlesource.com/c/public/gem5/+/40622
allows units to be shown in stats dump, the units in stats
descriptions are nolonger necessary. This change removes units
from stats descriptions. However, for units that are multiples
of a supported unit (e.g. MegaBytes), the units in the descriptions
are kept until unit prefixes are supported.

Change-Id: I4d87139290a8458e87da776e4328edbd6c224546
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40655
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

base-stats: Print Units in Stats dump

Change-Id: I8fba4f19805c3149175ff730d014383dcaa1bf81
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40622
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Change warmupCycle stat to warmupTick

Change-Id: I96399dc5c062479049e7bf0de91d9f4f97903c43
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40575
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

cpu: Add Units to cpu stats

Change-Id: I387b2e9f6ecf62757242056f732bd443c457ebea
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

learning-gem5: Add units to stats

Change-Id: Iaff6c19b0b87250d15f5afb0763680fafe782d52
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39417
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-arm,arch-riscv,arch-x86: Add units to stats

Change-Id: I6bf506c223207306d71511491e024546b209030f
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39416
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

dev,dev-arm: Add units to stats in /src/dev

Change-Id: I9d2449ef173f2f467717a9d233aef8d9a2f43f26
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39415
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

sim: Add units to src/sim

Change-Id: I5fa147aa1319d62be1790bbd74fd097ac566f808
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39296
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

mem: Add Units to mem stats

Add units to mem stats except mem-ruby stats

Change-Id: Iab214b5d08eb1accc2b35af0c3aed7d30df5b5f3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39276
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,mem: Converting stats to supported units

There are several stats having unit being a multiple of supported
units. This change makes the following conversions:
  * MiB/s -> bytes/s
  * percentage -> ratio

Change-Id: I9832796e87698daa7f87f91fa39ce40bbf92e737
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41013
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

mem: Fix/Improve stats in src/mem

* Improved/Fixed the stat description of several stats.
* Fixed the value assigned to `warmupCycle` stat of cache tags,
it was set to curTick().
* Use ADD_STAT in CacheCmdStats.

Change-Id: Iabff7d42318fcc73df79ee7f3c5430f4c45555e5
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39975
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base-stats: Add Units to Stats

This commit adds an option to add SI and its derived units to stats.

Units are now the third parameter of every Stat class constructor.

The following are convenient macros that could be used to add units
to stats,
   * UNIT_CYCLE: represents clock cycles.
   * UNIT_TICK: represents the count of gem5's Tick.
   * UNIT_SECOND: represents the base unit of time defined by SI.
   * UNIT_BIT: represents the number of computer bits.
   * UNIT_BYTE: represents 8 bits.
   * UNIT_VOLT: a SI derived unit measuring potential difference.
   * UNIT_JOULE: represents joule, a unit of energy, as defined by SI.
   * UNIT_WATT: represents 1 watt, where 1 watt = 1 joule / second.
   * UNIT_CELSIUS: represents 1 Celsius degree as defined by SI.
   * UNIT_RATE(T1, T2): represents the unit of a quantity of T1 divided
                        by a quantity of T2.
   * UNIT_RATIO: represents the unit of a quantity of unit T divided by
                 a quantity of unit T.
   * UNIT_UNSPECIFIED: the unit of the stat is unspecified. This type of
                       unit is mainly for backward compatibility. Newly
                       introduced stats should have the units specified.

This commit also alters the behavior of the ADD_STAT macro.
Specifically, ADD_STAT syntax is unchanged, but the unit of the stat
is hardcoded to be UNIT_UNSPECIFIED.

link: https://gem5.atlassian.net/browse/GEM5-849
This change is an effort towards supporting new stats schema:
https://github.com/gem5/stats-schema

Change-Id: I791704a6c4d9e06332797dbfc5eb611cb43f4710
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38855
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Track misc regs in vectors in the O3 CPU instruction class.

Most instructions won't actually write to misc regs, so the overhead
should be quite small, particularlly compared to the other overheads in
the O3.

Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38388
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Track flat register indices in the Minor CPU with a vector.

That avoids having to know the maximum number of dest registers there
can be in any instruction, and will likely not affect the performance of
the Minor CPU overall.

Change-Id: I4e49695ba06365d52eb4ce128d5cbb30db665bd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38387
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Factor MaxInst(SrcDest)Regs out of the trace CPU.

Manage register and ROB dependencies using lists instead of arrays to
better support random removals, and avoid having to know the global
maximum number of registers in an instruction.

Change-Id: Ie9f30c61bac52ad31745a1011f62c95622908d2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38386
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add XOR and modulo operator to ChannelAddr

Channel address class did not offer bitwise
XOR and modulo operation. These two functions
where now added to the ChannelAddr class.

Change-Id: I02a5e49e9700cc5283415c921a25989a130e5d07
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39235
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Get rid of the IsConforming type trait template.

The idea of this template was to distinguish types which should
grow/shrink based on the native size of the ABI in question. Or in other
words, if the ABI was 32 bit, the type should also be 32 bit, or 64 bit
and 64 bit.

Unfortunately, I had intended for Addr to be a conforming type (since
local pointers would be conforming), but uint64_t not to be. Since Addr
is defined as a typedef of uint64_t, the compiler would make *both*
types conforming, giving incorrect behavior on 32 bit systems.

Local pointers will need to be handled in a different way, likely with
the VPtr template, so that they will be treated correctly and not like
an explicitly 64 bit data type.

Change-Id: Idfdd5351260b48bb531a1926b93e0478a297826d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40495
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>