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2021-01-28	Jean-Paul Chaput	Working bench design with SRAM in top block.	commit \| commitdiff \| tree
2021-01-27	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2021-01-27	Jean-Paul Chaput	Pinmux loading is now integrated in Coriolis.	commit \| commitdiff \| tree
2020-11-30	Jean-Paul Chaput	Added experiments11, base for full chip with FlexLib...	commit \| commitdiff \| tree
2020-11-02	Jean-Paul Chaput	Completed experiment10, adder with JTAG (dual clocks...	commit \| commitdiff \| tree
2020-10-25	Jean-Paul Chaput	Added one-clock generated add.vst.	commit \| commitdiff \| tree
2020-10-25	Jean-Paul Chaput	Experiment10 switched to the new chip2core module.	commit \| commitdiff \| tree
2020-09-30	Jean-Paul Chaput	URL of submodule pinmux needs to use ssh/port 922.	commit \| commitdiff \| tree
2020-09-15	Jean-Paul Chaput	Use Yosys flattening for top blocks.	commit \| commitdiff \| tree
2020-09-14	Jean-Paul Chaput	Configuration updated for test of HFNS.	commit \| commitdiff \| tree
2020-08-12	Jean-Paul Chaput	Added doDesignFlat.py to P&R issuer in a flat way.	commit \| commitdiff \| tree
2020-08-11	Jean-Paul Chaput	Correct taking in accounts of the parameters settings.	commit \| commitdiff \| tree
2020-08-07	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	commit \| commitdiff \| tree
2020-08-07	Jean-Paul Chaput	Use of CfgCache. Little beautificaton of doDesign.py	commit \| commitdiff \| tree
2020-08-03	Jean-Paul Chaput	Fisrt attempt at floorplaning test_issuer.	commit \| commitdiff \| tree
2020-06-06	Jean-Paul Chaput	Test of the FU-FU matrix 30x30 with Coriolis matrixplacer.	commit \| commitdiff \| tree
2020-04-20	Jean-Paul Chaput	Forgot to witre about block rotation.	commit \| commitdiff \| tree
2020-04-20	Jean-Paul Chaput	Optimized (datapath) placement and direct place.	commit \| commitdiff \| tree
2020-03-04	Jean-Paul Chaput	Correct configuration for fpmul64.	commit \| commitdiff \| tree

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