| 2021-12-13 |
Luke Kenneth Casson... | request a flush of icache to clear the instruction...
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | fix test_loadstore1.py with MSR=PR/DR
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | set pr=0 because privileged mode is pr=0 not pr=1
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | add in missing MSRSpec import
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | commented-out code
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | fix up pr/dr/sf in PortInterfaceBase
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | pass in new MSRSpec to test_loadstore1.py not msr_pr=1
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | convert PortInterfaceBase to pass msr not msr_pr
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | convert LoadStore1 to new msr.pr/dr/sf
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | add msr to MMU Op Subset record
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | still have to import MSRSpec
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | connect up PortInterface priv_mode, virt_mode and mode_32bit
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | construct an MSRSpec in PortInterfaceBase (not used...
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | whoops wrong variable names
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | rename msr_pr to priv_mode in LDSTCompUnit
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | TODO comments about using MSRspec
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | change PortInterface naming to msr not msr_pr in set_wr_addr
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | set and reset instruction fault so it does not occur...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | when an exception happens, if it is a fetch_failed...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | delay MMU LOOKUP done by one clock so that the exception...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | bring MMU exception out where AllFunctionUnits (and...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | bring exception out from MMU FSM, correct "done"
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | add LDSTException output to MMU
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | drat, a test inverting the instruction made it into...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | starting to hack in fetch failed (including OP_FETCH_FAILED)
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | print debugs established that when a wb_get memory...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | set fetch_failed into PowerDecoder2 combinatorially
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | in a terrible botched way, get at I-Cache and set it up
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | fix bug in unit test, forgot that wb_get mem dict is...
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | get FetchUnitInterface I-Cache test working (sort-of)
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | comment out broken test
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | whoops forgot to add pspec
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | add start of test_loadstore1_ifetch_unit_interface()
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | connect up I-Cache to FetchUnitInterface
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | add new ConfigFetchUnit option "mmu_cache_wb" which...
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | add some examination of the failed-fetched instruction
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | add some debug string info to gtkwave
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | add I-Cache to FSM local variables
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | wire fetch_failed from I-Cache to PowerDecoder2
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | make icache accessible to core, working back to TestIssuer
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | include SPR.TB in SPR FU
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | got fed up of staring at magic constants in the MMU
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add special pagetable to ifetch_invalid with execute...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | do not try priv_mode on the instruction fetch (not...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add an example pagetable where executable permission...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | check that no exception occurs in the virtual-memory...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add OP_FETCH_FAILED to MMU Function Unit
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | make LoadStore1 intsr_fault a "captured flag" - strictly...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | remove MSR and add CIA to MMU Input Record
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add instr_fault to LoadStore1 FSM
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add new PortInterfaceBase external_busy() option
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | complete the i-cache fetch through the MMU, including...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | set separate "iside" signal in LoadStore1 to not confuse it
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | start extending icache loadstore test
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | whoops another serious error in the CacheTagArray
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add first i-cache fetch (non-virtual), no MMU lookup...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add in I-Cache into LoadStore1 - presently unused ...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add discussion links and bugreport
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | invert mmureq statements
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | submodule tidyup
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | tidyup, comments
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | debug print
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | another major bug, CacheTagArray valid was only 1 bit...
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | tidyup: move hit_set to DCachePendingHit in dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | dcache.py tidyup
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | rename dtlb to dtlb_valid and tidyup
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | convert TLBArray to TLBValidArray
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | convert DTLBUpdate to use a pair of Memorys
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | more signals local to DTLBUpdate
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | more signals local to DTLBUpdate
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | update DTLBUpdate to reflect internal API now
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | ooo nasty bug. used tlb_hit.way instead of tlb_hit...
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | move DTLB Tags/Valids/PTEs into DTLBUpdate module
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | start moving TLBArray into DTLBUpdate
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | PLRUs were selecting an output index, only one selected
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | repeated copies of read/write addr/sel to Cache SRAMs
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | move bank of PLRUs to their own submodule in both dcache...
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use binary-to-unary encoders in dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | global (one) do_read signal in cache_rams dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use one-hot binary-to-unary in dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use i_in.req to gate hit_way via Decoder in icache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | use Decoder (binary-to-unary) in icache.py to deal...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use unary encoding (one-hot) for replace_way hit_way...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | whitespace and minor cleanup of D-Cache
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | more use of TLBHit Record in D-Cache
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | correct tlb_hit_way and index sizes, use TLBHit Record...
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use TLBRecord in D-Cache for which TLB is selected
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | split out TLBRecord, correct number of valid bits
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record in DCache for TLB
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record in D-Cache Cache Tags
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record for I-Cache Cache Tag/Valid
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | use Record for ICache TLB
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | sorting out test_mmu_dcache.py to use wb_get
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | convert icache.py to standard wishbone Interface
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commit | commitdiff | tree |
| 2021-12-05 |
Luke Kenneth Casson... | fake up wishbone stall signal in icache.
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commit | commitdiff | tree |
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