soc.git
2021-02-28 Luke Kenneth... add SVP64 RM sub-field enums
2021-02-28 Luke Kenneth... move SVP64 Extra decoders to separate module
2021-02-28 Luke Kenneth... fix syntax error
2021-02-28 Luke Kenneth... move SVP64PrefixDecoder to separate module
2021-02-28 Luke Kenneth... add PowerDecoder.no_in_vec
2021-02-28 Luke Kenneth... add svp64_instrs to power_svp64
2021-02-28 Tobias Platenfix Bug 607 - unnecessary code added related to MMU...
2021-02-28 Tobias Platenfix Bug 603 - use SPR names/numbers from sprs.csv
2021-02-27 Luke Kenneth... use PowerDecoder2.no_out_vec instead of manual vector...
2021-02-27 Luke Kenneth... add corresponding VL=0 unit test as from 161b7d67b...
2021-02-27 Cesar StraussAdd traces for the new FSM
2021-02-26 Cesar StraussAdd a vector case with VL == 0
2021-02-26 Luke Kenneth... comment on CoreState
2021-02-26 Luke Kenneth... remove sv_changed input to fetch_fsm, add it to issue_f...
2021-02-26 Luke Kenneth... moving new_svstate and update_svstate into issue FSM...
2021-02-26 Luke Kenneth... move fetch_insn_o into issue_fsm TestIssuer
2021-02-26 Luke Kenneth... add comments, missing that VL loop ends after execution...
2021-02-26 Cesar StraussImplement a decode/issue FSM between fetch and execute
2021-02-24 Tobias Platenwb_get: write outputs to seperate logfile too
2021-02-24 Tobias Platenupdate mmu testcase
2021-02-24 Tobias Platentest_runner.py: add needed imports
2021-02-24 Luke Kenneth... add comments explaining split
2021-02-24 Luke Kenneth... move DecodeCROut/In (at last) out of PowerDecoderSubset...
2021-02-24 Luke Kenneth... start making write_cr0 independent of DecodeCROut
2021-02-23 Tobias Platendeduplicate
2021-02-23 Luke Kenneth... add note that SVSTATE has changed, this will allow...
2021-02-22 Cesar StraussFix typo when calculating PowerDecoder2.no_out_vec
2021-02-22 Luke Kenneth... move setting of NIA into fetch FSM in TestIssuer
2021-02-22 Luke Kenneth... whoops
2021-02-22 Luke Kenneth... moving PC-setting (NIA) out of execute_fsm in TestIssuer
2021-02-22 Luke Kenneth... rename inter-FSM handshake signals in TestIssuer
2021-02-21 Luke Kenneth... err trying to put in some FSM handshake signals, gettin...
2021-02-21 Luke Kenneth... comment for where SVSTATE FSM should go
2021-02-21 Luke Kenneth... add CR out vector detection to PowerDecoder2 no_out_vec
2021-02-21 Cesar StraussThe field selection function was moved to nmutil.util
2021-02-21 Cesar StraussHide the register augmentation traces by default
2021-02-21 Luke Kenneth... move execute_fsm to separate function in TestIssuer
2021-02-21 Luke Kenneth... move fetch_fsm to separate function in TestIssuer
2021-02-21 Luke Kenneth... add JTAG enable/disable of 4k SRAMs
2021-02-21 Cesar StraussThe new version of "sel" is smart enough to find a...
2021-02-21 Luke Kenneth... add comments for Mode field in SVP64Asm
2021-02-21 Luke Kenneth... comments in SVP64RMFields
2021-02-21 Cesar StraussUse the new selection field function from nmutil
2021-02-21 Cesar StraussUse symbolic values as field sizes
2021-02-21 Cesar StraussReplace all hardcoded shifts into RM by usage of SVP64R...
2021-02-21 Luke Kenneth... create SVP64CROffs consts for when SVP64 Vector-of...
2021-02-20 Luke Kenneth... comments on sv.add. Rc=1 unit test
2021-02-20 Luke Kenneth... add in Vectorised CRs when Rc=1 into ISACaller
2021-02-20 Luke Kenneth... add CR1 to DecodeCRIn/Out
2021-02-20 Luke Kenneth... add some debug checking to get_pdecode_cr_out
2021-02-20 Luke Kenneth... add crossreference to bug #603
2021-02-20 Luke Kenneth... add more debug output to get_pdecode_cr_out
2021-02-20 Cesar StraussActually forward the field width to field_slice()
2021-02-20 Cesar StraussAssemble the SV64 prefix from its subfields using SVP64...
2021-02-20 Luke Kenneth... start on CRs in SVP64 mode
2021-02-20 Luke Kenneth... fix SVP64Asm Rc=1 assembly
2021-02-20 Luke Kenneth... add black-box attribute to 4k SRAM cell
2021-02-20 Cesar StraussFix more MSB0 issues in comments
2021-02-20 Cesar StraussReplace more hardcoded constants with symbolic field...
2021-02-20 Luke Kenneth... increment CRs based on srcstep, see what happens
2021-02-20 Luke Kenneth... add litex wishbone interconnect to 4x 4k SRAMs
2021-02-20 Luke Kenneth... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer...
2021-02-20 Luke Kenneth... add option for QTY 4x 4k SRAM blocks (not added yet...
2021-02-20 Luke Kenneth... add Wishbone-wrapped SPBlock_512W64B8W
2021-02-20 Luke Kenneth... whoops set ROM to none by mistake
2021-02-20 Luke Kenneth... whoops spelling error
2021-02-20 Luke Kenneth... add (unused) code for writing out SVSTATE in TestIssuer
2021-02-20 Luke Kenneth... correct arguments, set microwatt_mmu=True, pass in...
2021-02-20 Luke Kenneth... minor whitespace cleanup
2021-02-20 Luke Kenneth... remove massive code-duplication, move simple "self...
2021-02-20 Tobias Platenmmu testcase: set MMU SPRs
2021-02-20 Tobias Platenadd rom debugger
2021-02-20 Tobias Platenadd mmu rom testcase
2021-02-18 Tobias Platenmmu: remove TestMemory
2021-02-17 Luke Kenneth... declare blank classes SPEC and EXTRA2 to add MSB-to...
2021-02-17 Cesar StraussUse subfield bit selection to extract the RM SVP64...
2021-02-17 Cesar StraussReplace MSB-i by symbolic subfield indices and selectors
2021-02-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-17 Tobias Platenadd wishbone signals to gtkwave output
2021-02-17 Cesar StraussAdd the SVSTATE traces to GTKWave to allow debugging...
2021-02-17 Cesar StraussInitialize the core SVSTATE from the corresponding...
2021-02-17 Cesar StraussRevert "Setup SVSTATE, from the test settings, at the...
2021-02-17 Cesar StraussAdd a function to select bits from a signal into a...
2021-02-17 Luke Kenneth... fix reg read/write in ISACaller, PowerDecoder2 handles...
2021-02-17 Cesar StraussAdd a case for checking the EXTRA field and register...
2021-02-17 Cesar StraussAdd traces to debug SVP64 prefix decoding issues
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start
2021-02-16 Cesar StraussFix MSB0 issues for SVP64
2021-02-16 Tobias Platenmmureq handling
2021-02-16 Tobias Platendcache error handling
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-16 Luke Kenneth... ordering wrong on svstate in ISACaller
2021-02-16 Luke Kenneth... adapt botchify so it can be used for 31- or 15- etc...
2021-02-16 Luke Kenneth... add indicator to PowerDecoder2 when no outputs are...
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it...
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Cesar StraussShow traces for the register numbers of the current...
2021-02-14 Cesar StraussFix width of the "extra" input on the Extra decoder
next