soc.git
2021-02-20 Luke Kenneth... start on CRs in SVP64 mode
2021-02-20 Luke Kenneth... fix SVP64Asm Rc=1 assembly
2021-02-20 Luke Kenneth... add black-box attribute to 4k SRAM cell
2021-02-20 Cesar StraussFix more MSB0 issues in comments
2021-02-20 Cesar StraussReplace more hardcoded constants with symbolic field...
2021-02-20 Luke Kenneth... increment CRs based on srcstep, see what happens
2021-02-20 Luke Kenneth... add litex wishbone interconnect to 4x 4k SRAMs
2021-02-20 Luke Kenneth... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer...
2021-02-20 Luke Kenneth... add option for QTY 4x 4k SRAM blocks (not added yet...
2021-02-20 Luke Kenneth... add Wishbone-wrapped SPBlock_512W64B8W
2021-02-20 Luke Kenneth... whoops set ROM to none by mistake
2021-02-20 Luke Kenneth... whoops spelling error
2021-02-20 Luke Kenneth... add (unused) code for writing out SVSTATE in TestIssuer
2021-02-20 Luke Kenneth... correct arguments, set microwatt_mmu=True, pass in...
2021-02-20 Luke Kenneth... minor whitespace cleanup
2021-02-20 Luke Kenneth... remove massive code-duplication, move simple "self...
2021-02-20 Tobias Platenmmu testcase: set MMU SPRs
2021-02-20 Tobias Platenadd rom debugger
2021-02-20 Tobias Platenadd mmu rom testcase
2021-02-18 Tobias Platenmmu: remove TestMemory
2021-02-17 Luke Kenneth... declare blank classes SPEC and EXTRA2 to add MSB-to...
2021-02-17 Cesar StraussUse subfield bit selection to extract the RM SVP64...
2021-02-17 Cesar StraussReplace MSB-i by symbolic subfield indices and selectors
2021-02-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-17 Tobias Platenadd wishbone signals to gtkwave output
2021-02-17 Cesar StraussAdd the SVSTATE traces to GTKWave to allow debugging...
2021-02-17 Cesar StraussInitialize the core SVSTATE from the corresponding...
2021-02-17 Cesar StraussRevert "Setup SVSTATE, from the test settings, at the...
2021-02-17 Cesar StraussAdd a function to select bits from a signal into a...
2021-02-17 Luke Kenneth... fix reg read/write in ISACaller, PowerDecoder2 handles...
2021-02-17 Cesar StraussAdd a case for checking the EXTRA field and register...
2021-02-17 Cesar StraussAdd traces to debug SVP64 prefix decoding issues
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start
2021-02-16 Cesar StraussFix MSB0 issues for SVP64
2021-02-16 Tobias Platenmmureq handling
2021-02-16 Tobias Platendcache error handling
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-16 Luke Kenneth... ordering wrong on svstate in ISACaller
2021-02-16 Luke Kenneth... adapt botchify so it can be used for 31- or 15- etc...
2021-02-16 Luke Kenneth... add indicator to PowerDecoder2 when no outputs are...
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it...
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Cesar StraussShow traces for the register numbers of the current...
2021-02-14 Cesar StraussFix width of the "extra" input on the Extra decoder
2021-02-14 Cesar StraussFix conversion to MSB0
2021-02-14 Cesar StraussRemove obsolete comment
2021-02-14 Luke Kenneth... add comments to TestIssuer
2021-02-14 Luke Kenneth... add srcstep onto Vectorised GPRs in PowerDecoder2
2021-02-14 Luke Kenneth... add TestRunner comments
2021-02-14 Luke Kenneth... add Regfiles comments
2021-02-14 Luke Kenneth... add SVSTATE reading to TestIssuer
2021-02-14 Luke Kenneth... add SVSTATE to CoreState
2021-02-14 Luke Kenneth... add extra FSM explanatory comments to TestIssuer
2021-02-13 Luke Kenneth... use function for getting instruction from 32/64 bit...
2021-02-13 Cesar StraussFetch and decode the SVP64 prefix
2021-02-13 Tobias PlatenOP_TLBIE must in be instr_is_priv
2021-02-13 Tobias Platenkeep commits to under 80 chars
2021-02-13 Cesar StraussCheck the PC value at the end of each instruction
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case
2021-02-13 Cesar StraussFix imports and whitespace
2021-02-13 Luke Kenneth... update svp64 unit test comments
2021-02-13 Tobias Platenforward microwatt mmu specific SPR: PID and PRTBL
2021-02-13 Luke Kenneth... add SVP64 TestIssuer separate unit test
2021-02-13 Luke Kenneth... split out TestRunner into separate module
2021-02-13 Cesar StraussFix SVP64 translator to yield the unaltered instruction
2021-02-12 Luke Kenneth... add one SVP64 ALU test case to get started
2021-02-12 Luke Kenneth... add SVSTATE to TestCase infrastructure for use in TestI...
2021-02-12 Luke Kenneth... add skip of instruction if SVSTATE.VL=0 in ISACaller
2021-02-12 Luke Kenneth... validate all registers to make sure no damage occurs...
2021-02-12 Luke Kenneth... add srcstep and correct PC-advancing during Sub-PC...
2021-02-12 Luke Kenneth... comments
2021-02-12 Luke Kenneth... add in SVSTATE.srcstep update, loop from 0 to VL-1
2021-02-12 Luke Kenneth... allow PC to update by 8 in SVP64 mode
2021-02-12 Luke Kenneth... fix setting of SVSTATE.VL and MVL
2021-02-12 Luke Kenneth... add in SVSTATE to ISACaller, not used, just passed in
2021-02-11 Luke Kenneth... comments in TestIssuer for SVP64PrefixDecoder
2021-02-10 Luke Kenneth... add svp64 reg decode detection to ISACaller output
2021-02-10 Luke Kenneth... starting to add SVP64 register EXTRA-read and isvec...
2021-02-10 Luke Kenneth... comment update
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore
2021-02-09 colepoirierfix erroneous removal of proof* from experiment/formal...
2021-02-07 colepoirieradd skeleton implementation of experiment/formal/proof_...
2021-02-07 colepoiriericache.py fix formatting
2021-02-07 colepoirierModify experiment/formal/.gitignore because was prevent...
2021-02-06 Cesar StraussFix whitespace
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM
2021-02-05 Tobias Platenfix hanging simulation
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
2021-02-04 Tobias Platenupdate test_issuer_mmu_data_path.py to handle SPRs
2021-02-04 Tobias Platenpass SPR MicroOp to MMU function unit
2021-02-03 Luke Kenneth... nope - need it to be zero if not identified as svp64
2021-02-03 Luke Kenneth... actually no need to mux in the svp64_rm, just the id...
2021-02-03 Luke Kenneth... add SVP64PowerDecoder, extracts svp64 remap if correctl...
2021-02-01 Luke Kenneth... ISACaller, in svp64 mode, read the next 32 bits when...
2021-02-01 Tobias Platenextending the GTKWave document in test_issuer when...
2021-02-01 Luke Kenneth... sort out SelectableInt bit-ordering for identifying...
2021-02-01 Luke Kenneth... construct the assembly-code prefix and base v3.0B in...
2021-02-01 Cesar StraussAdd GTKWave document to test_issuer
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