projects / soc.git / shortlog
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
soc.git
2022-10-16 Cesar StraussMove test to expose bug in MultiCompUnit commit | commitdiff | tree
2022-10-12 Cesar StraussCheck invariant for instruction operands commit | commitdiff | tree
2022-10-12 Cesar StraussIf the ALU is idle, do not assert valid commit | commitdiff | tree
2022-10-09 Cesar StraussCount zero_a and imm_data.ok as masked read transactions commit | commitdiff | tree
2022-10-09 Cesar StraussDon't issue while busy commit | commitdiff | tree
2022-10-08 Cesar StraussAdd count of masked reads commit | commitdiff | tree
2022-10-08 Cesar StraussAdd ALU read transaction counter commit | commitdiff | tree
2022-10-08 Cesar StraussAdd ALU write transaction counter commit | commitdiff | tree
2022-10-08 Cesar StraussAdd write transaction counter commit | commitdiff | tree
2022-10-05 Cesar StraussFix duplicate line (copy & paste error) commit | commitdiff | tree
2022-10-01 Cesar StraussAdd counter for operand reads commit | commitdiff | tree
2022-10-01 Cesar StraussAvoid toggling go_i when rel_o is low commit | commitdiff | tree
2022-10-01 Cesar StraussLeave shadow / die proof for last commit | commitdiff | tree
2022-10-01 Cesar StraussStart of formal proof of MultiCompUnit commit | commitdiff | tree
2022-08-16 Jacob Lifshaychange goldschmidt_div_sqrt to use nmutil.plain_data... commit | commitdiff | tree
2022-08-14 Luke Kenneth... grr not a yield function commit | commitdiff | tree
2022-08-14 Luke Kenneth... add get_fpregs stub function to HDLstate commit | commitdiff | tree
2022-07-06 Luke Kenneth... update pinmux submodule, rename to "fabric" commit | commitdiff | tree
2022-07-06 Luke Kenneth... add fabric compatibility mode commit | commitdiff | tree
2022-07-05 Luke Kenneth... MulOutputData was only 64-bit output not 128-bit commit | commitdiff | tree
2022-07-04 Luke Kenneth... add signal for resetting trap internal state (kaivb... commit | commitdiff | tree
2022-07-04 Luke Kenneth... set msr_o.data not msr_o Record in trap main_stage.py commit | commitdiff | tree
2022-06-26 Luke Kenneth... adapt TRAP function in main state pipeline to put KAIVB commit | commitdiff | tree
2022-06-26 Luke Kenneth... store KAIVB SPR 850 in TRAP Pipeline commit | commitdiff | tree
2022-06-26 Luke Kenneth... reduce icache/dcache TLB sizes commit | commitdiff | tree
2022-06-26 Luke Kenneth... update trap test_pipe_caller.py to use up-to-date test... commit | commitdiff | tree
2022-06-26 Luke Kenneth... missing module argument to TestRunner execute commit | commitdiff | tree
2022-06-26 Luke Kenneth... convert trap test_pipe_caller.py to consistent format commit | commitdiff | tree
2022-05-23 Andrey MiroshnikovChange usage of WB sel for individual control commit | commitdiff | tree
2022-05-01 Luke Kenneth... split out front of div into separate stage, still too... commit | commitdiff | tree
2022-04-30 Luke Kenneth... add missing module commit | commitdiff | tree
2022-04-30 Luke Kenneth... split off CR0/XER production in DIV Function Unit into... commit | commitdiff | tree
2022-04-30 Luke Kenneth... clear out DEC in core.cur_state.dec due to spurious... commit | commitdiff | tree
2022-04-30 Cesar StraussImplement transparent read port option on the XOR wrapp... commit | commitdiff | tree
2022-04-29 Jacob Lifshayfix waay-too-precise error requirements commit | commitdiff | tree
2022-04-29 Luke Kenneth... add option to set small cache sizes in commit | commitdiff | tree
2022-04-29 Jacob Lifshayadd comment commit | commitdiff | tree
2022-04-29 Jacob Lifshayfix so HDL works for 5, 8, 16, 32, and 64-bits. commit | commitdiff | tree
2022-04-29 Jacob LifshayHDL works for io_width=5 commit | commitdiff | tree
2022-04-28 Cesar StraussTest simultaneous transparent reads and partial writes commit | commitdiff | tree
2022-04-28 Jacob Lifshayadd docs for clz commit | commitdiff | tree
2022-04-28 Jacob Lifshayadd WIP HDL version of goldschmidt division -- it's... commit | commitdiff | tree
2022-04-28 Luke Kenneth... notes added to setup.py - absolute paranoia is needed on commit | commitdiff | tree
2022-04-28 Jacob Lifshaymove GoldschmidtDivState commit | commitdiff | tree
2022-04-28 Jacob Lifshayadd FIXME comments commit | commitdiff | tree
2022-04-28 Jacob Lifshayadd the goldschmidt sqrt/rsqrt algorithm, still need... commit | commitdiff | tree
2022-04-27 Jacob Lifshayswitch cached-property dependency to using libre-soc... commit | commitdiff | tree
2022-04-27 Jacob Lifshayimproved goldschmidt division algorithm parameter optim... commit | commitdiff | tree
2022-04-27 Jacob Lifshaysplit out non-derived params into separate class withou... commit | commitdiff | tree
2022-04-27 Jacob Lifshaysplit out n_hat as separate property commit | commitdiff | tree
2022-04-27 Jacob Lifshayadd default_cost_fn commit | commitdiff | tree
2022-04-27 Jacob Lifshaymove GoldschmidtDivParams.get to bottom of class commit | commitdiff | tree
2022-04-27 Jacob Lifshayrename _goldschmidt_div_ops to GoldschmidtDivState... commit | commitdiff | tree
2022-04-26 Jacob Lifshaygoldschmidt division works! still needs better paramete... commit | commitdiff | tree
2022-04-26 Jacob Lifshayfix goofed __init__.py file name commit | commitdiff | tree
2022-04-25 Jacob Lifshayworking on goldschmidt_div_sqrt.py commit | commitdiff | tree
2022-04-25 Jacob Lifshayadd cached_property dependency commit | commitdiff | tree
2022-04-23 Jacob Lifshayworking on goldschmidt division algorithm commit | commitdiff | tree
2022-04-22 Luke Kenneth... whitespace commit | commitdiff | tree
2022-04-22 Jacob Lifshayadd WIP goldschmidt division algorithm commit | commitdiff | tree
2022-04-17 Cesar StraussImplement a 1W/1R register file, XOR style commit | commitdiff | tree
2022-04-17 Cesar StraussFormal proof of pseudo 1W/2R SRAM commit | commitdiff | tree
2022-04-17 Cesar StraussAdd transparent option for the full read port commit | commitdiff | tree
2022-04-17 Cesar StraussImplement a pseudo 1W/2R memory commit | commitdiff | tree
2022-04-16 Luke Kenneth... reduce dcache/icache number of ways, to fit into ECP5... commit | commitdiff | tree
2022-04-16 Tobias Platenpart two of issuer_fix: read pspec.microwatt_old and... commit | commitdiff | tree
2022-04-16 Cesar StraussCheck non-transparent 1W/1R SRAM wrapper commit | commitdiff | tree
2022-04-16 Cesar StraussEnable read port for non-transparent memories commit | commitdiff | tree
2022-04-16 Tobias PlatenMerge ssh://git.libre-riscv.org:922/soc commit | commitdiff | tree
2022-04-16 Tobias Platenpart one of issuer_fix: add parameter to issuer_verilog.py commit | commitdiff | tree
2022-04-16 Cesar StraussAdd port declarations to the SRAM wrappers commit | commitdiff | tree
2022-04-16 Cesar StraussChange write lane signal from one-hot to binary commit | commitdiff | tree
2022-04-16 Luke Kenneth... whoops, WBASyncBridge ack signal not wired up! commit | commitdiff | tree
2022-04-16 Luke Kenneth... select width is data_width // data granularity. commit | commitdiff | tree
2022-04-16 Cesar StraussSynchronize LVT state, completing the induction proof commit | commitdiff | tree
2022-04-16 Cesar StraussSync proof state with downstream memories commit | commitdiff | tree
2022-04-16 Luke Kenneth... put the old microwatt compatibility back commit | commitdiff | tree
2022-04-16 Luke Kenneth... blegh. commit | commitdiff | tree
2022-04-15 Cesar StraussComplete moving the induction support into the DUT commit | commitdiff | tree
2022-04-15 Cesar StraussFix incorrect signal widths commit | commitdiff | tree
2022-04-15 Cesar StraussMove part of formal proof to the implementation commit | commitdiff | tree
2022-04-14 Luke Kenneth... add option Spec to XICS ICP/ICS to be able to activate... commit | commitdiff | tree
2022-04-14 Luke Kenneth... move IRQLine out because that makes soc dependent on... commit | commitdiff | tree
2022-04-14 Luke Kenneth... 80 char limit, remove creation of stall from ack/cyc... commit | commitdiff | tree
2022-04-14 Raptor Engineering... wb_async: Allow different feature fields for master... commit | commitdiff | tree
2022-04-14 Raptor Engineering... Add separate memory clock register to SYSCON commit | commitdiff | tree
2022-04-12 Tobias Platenissuer.py: add microwatt_old and microwatt_debug options commit | commitdiff | tree
2022-04-11 Raptor Engineering... Separate core and nest clocks in Microwatt SYSCON commit | commitdiff | tree
2022-04-11 Raptor Engineering... Add initial wrapper for Wishbone asynchronous bridge... commit | commitdiff | tree
2022-04-10 Cesar StraussBegin a formal proof of the LVT-based 1W/1R wrapper commit | commitdiff | tree
2022-04-10 Cesar StraussImplement 1W/1R with a transparent (or not) read port. commit | commitdiff | tree
2022-04-10 Cesar StraussImplement a true 1W/1R memory from 1RW blocks commit | commitdiff | tree
2022-04-09 Luke Kenneth... add a new make target for setting coldboot firmware... commit | commitdiff | tree
2022-04-08 Luke Kenneth... syntax error commit | commitdiff | tree
2022-04-08 Luke Kenneth... add dram to SysCon commit | commitdiff | tree
2022-04-08 Luke Kenneth... add SPI offset to microwatt syscon commit | commitdiff | tree
2022-04-06 Luke Kenneth... only add clock-settings on ECP5 due to special SPI... commit | commitdiff | tree
2022-04-04 Luke Kenneth... add tempfile to uart16550 wrapper which defines DATA_BU... commit | commitdiff | tree
2022-04-04 Luke Kenneth... disable sphinx verilg-diagrams for now commit | commitdiff | tree
2022-04-04 Luke Kenneth... allow direction-setting on each of dq0-3 in Tercel... commit | commitdiff | tree
next