soclayout.git
2020-03-18 Jock TannerSimplify pin creation.
2020-03-18 Jock TannerParameterize bit width.
2020-03-17 Luke Kenneth... reposition add and sub, and do place in the *middle...
2020-03-16 Luke Kenneth... add mksym.sh
2020-03-16 Jock TannerGeneralize layer creation/retrieval.
2020-03-16 Jock TannerReturn unused layers.
2020-03-16 Jock TannerFix import.
2020-03-14 Jock TannerDelete stale code.
2020-03-13 Jock TannerFix style, imports, stale code.
2020-03-13 Jock TannerAdd experiment #7.
2020-03-06 Luke Kenneth... add ioring.py (forgot about)
2020-03-06 lkclwhoops removed mksym.sh when shouldnt
2020-03-06 lkclinteresting: using nsxlib in experiment/ never terminates
2020-03-06 lkclexperiment2 experimentation...
2020-03-06 lkclremove mksym.sh from low-level
2020-03-04 Luke Kenneth... add cmos to mksym.sh, disable YOSYS_FLATTEN
2020-03-04 Jean-Paul ChaputCorrect configuration for fpmul64.
2020-03-02 Luke Kenneth... add fpmul64.il test, to see how long it takes (10 minut...
2020-03-01 Luke Kenneth... managed to hack something together to get alu_hier...
2020-02-28 Luke Kenneth... add alu_hier place/route, partially works
2020-02-28 Luke Kenneth... add sub function (class-ish form)
2020-02-28 Luke Kenneth... successful ring created around add.ap
2020-02-28 Luke Kenneth... hmm still not adding traces
2020-02-28 Luke Kenneth... add VIA but metal not working yet
2020-02-28 Luke Kenneth... move add and sub, shrink alu_hier box
2020-02-27 Luke Kenneth... place and route alu_hier, not quite working yet
2020-02-27 Luke Kenneth... do sub layout as well
2020-02-27 Luke Kenneth... "UnManaged Configuration [16843009] = [1+1+0+1,1+0...
2020-02-27 Luke Kenneth... try adding short track manually (doesnt work)
2020-02-27 Luke Kenneth... getting closer to connecting at edge
2020-02-27 Luke Kenneth... successful route but still 40L off the top
2020-02-27 Luke Kenneth... overlap error in routing (two connections on same...
2020-02-26 Luke Kenneth... more experimenting, got cell down to smallest size...
2020-02-26 Luke Kenneth... segfault in pyDoAlu16.py
2020-02-26 Luke Kenneth... experiment with subtractor
2020-02-25 Luke Kenneth... add first experimental hierarchical place/route
2020-02-25 Luke Kenneth... add experiment5
2020-02-25 Luke Kenneth... add clk and ck so that ck is recognised for routing
2020-02-24 Luke Kenneth... add make view
2020-02-24 Luke Kenneth... bit more experimenting making an ioring around an adder
2020-02-24 Luke Kenneth... make example as close to adder benchmark as possible
2020-02-24 Luke Kenneth... simplify experiment4 to an adder, similar to adder...
2020-02-24 Luke Kenneth... add mksyms.sh
2020-02-24 Luke Kenneth... whoops yes use clocktree
2020-02-24 Luke Kenneth... add missing mksym.sh
2020-02-24 Luke Kenneth... continue experimentation
2020-02-23 Luke Kenneth... add sm3 to nets
2020-02-22 Luke Kenneth... correct nets for experiment2
2020-02-22 Luke Kenneth... track down module in which vdd / vss error exists ...
2020-02-22 Luke Kenneth... remove working code, shrink "fail" case
2020-02-22 Luke Kenneth... add test_partsig.py directly to experiment2
2020-02-22 Luke Kenneth... add ioring experiment
2020-02-22 Luke Kenneth... add sim just to see if anything happens
2020-02-22 Luke Kenneth... move Makefile3/4 to experiments3
2020-02-22 Luke Kenneth... move part_sig_add to its own directory
2020-02-22 Luke Kenneth... move alu_hier to own directory
2020-02-22 Luke Kenneth... change coriolis settings, logmode true
2020-02-21 Luke Kenneth... add extra gitignores
2020-02-21 Luke Kenneth... add path helpers sys libraries
2020-02-21 Luke Kenneth... add git ignore file
2020-02-21 Luke Kenneth... wrong script name
2020-02-21 Luke Kenneth... remove synthesise-yosys.mk use alliance one
2020-02-21 Luke Kenneth... add GND/PWR to see what happens in settings.py
2020-02-21 Luke Kenneth... reduce pmask to stop unconnected bits
2020-02-21 Luke Kenneth... use alternative experimental class TestAddMod2
2020-02-20 Luke Kenneth... fix mask width
2020-02-20 Luke Kenneth... add Makefile3
2020-02-20 Luke Kenneth... add second Makefile
2020-02-20 Luke Kenneth... move part_sig_add name
2020-02-20 Luke Kenneth... run alu_hier.py instead of alu.py (works)
2020-02-20 Luke Kenneth... remove clock
2020-02-19 Luke Kenneth... remove clock, use rename on clk in settings
2020-02-19 Luke Kenneth... increase etesian, set clock to clk
2020-02-19 Luke Kenneth... use simpler alu rather than alu_hier
2020-02-19 Luke Kenneth... add clocks and reset and add alu.py as well
2020-02-19 Luke Kenneth... replace part_sig_add with simpler design
2020-02-19 Luke Kenneth... add alu_hier.py example
2020-02-19 Luke Kenneth... replace VLOG with ILANG
2020-02-19 Luke Kenneth... start running and debugging
2020-02-19 Luke Kenneth... try symlink to mk fragments
2020-02-15 Luke Kenneth... remove whitespace
2020-02-15 Tobias Platenyosys example makefile
2020-02-14 Luke Kenneth... add synthesis-yosys.mk with ilang substituted
2020-02-14 Tobias Platenfirst example code
2020-02-11 Luke Kenneth... first empty commit