gem5.git
2021-02-15 Sandipan Dasarch-power: Add zero count instructions
2021-02-15 Sandipan Dasarch-power: Add sign-extend instructions
2021-02-15 Sandipan Dasarch-power: Fix disassembly for logical instructions
2021-02-15 Sandipan Dasarch-power: Fix logical instructions
2021-02-15 Sandipan Dasarch-power: Refactor logical instructions
2021-02-15 Sandipan Dasarch-power: Add character compare instructions
2021-02-15 Sandipan Dasarch-power: Fix disassembly for compare instructions
2021-02-15 Sandipan Dasarch-power: Fix compare instructions
2021-02-15 Sandipan Dasarch-power: Refactor compare instructions
2021-02-15 Sandipan Dasarch-power: Add fields for D and X form instructions
2021-02-15 Sandipan Dasarch-power: Add doubleword modulo instructions
2021-02-15 Sandipan Dasarch-power: Add word modulo instructions
2021-02-15 Sandipan Dasarch-power: Add doubleword divide-extended instructions
2021-02-15 Sandipan Dasarch-power: Add doubleword divide instructions
2021-02-15 Sandipan Dasarch-power: Add word divide-extended instructions
2021-02-15 Sandipan Dasarch-power: Add doubleword multiply-add instructions
2021-02-15 Sandipan Dasarch-power: Add fields for VA form instructions
2021-02-15 Sandipan Dasarch-power: Add doubleword multiply instructions
2021-02-15 Sandipan Dasarch-power: Add PC-relative arithmetic instructions
2021-02-15 Sandipan Dasarch-power: Add fields for DX form instructions
2021-02-15 Sandipan Dasarch-power: Fix disassembly for arithmetic instructions
2021-02-15 Sandipan Dasarch-power: Fix arithmetic instructions
2021-02-15 Sandipan Dasarch-power: Refactor arithmetic instructions
2021-02-15 Sandipan Dasarch-power: Add atomic load-store instructions
2021-02-15 Sandipan Dasarch-power: Add byte-reversed load-store instructions
2021-02-15 Sandipan Dasarch-power: Add doubleword load-store instructions
2021-02-15 Sandipan Dasarch-power: Fix disassembly for load-store instructions
2021-02-15 Sandipan Dasarch-power: Fix load-store instructions
2021-02-15 Sandipan Dasarch-power: Refactor load-store instructions
2021-02-15 Sandipan Dasarch-power: Add fields for DS form instructions
2021-02-15 Sandipan Dasarch-power: Fix precedence of register operands
2021-02-15 Sandipan Dasarch-power: Add TAR and associated instructions
2021-02-15 Sandipan Dasarch-power: Fix disassembly for branch instructions
2021-02-15 Sandipan Dasarch-power: Fix branch conditional instructions
2021-02-15 Sandipan Dasarch-power: Refactor branch instructions
2021-02-15 Sandipan Dasarch-power: Fix extended opcode based decoding
2021-02-15 Sandipan Dasarch-power: Add and rename some opcode fields
2021-02-15 Sandipan Dasarch-power: Refactor instruction decoding
2021-02-15 Sandipan Dasarch-power: Refactor special purpose registers
2021-02-15 Sandipan Dasarch-power: Use 64-bit registers and operands
2021-02-15 Daniel R. Carvalhobase: Add enum to_number tests
2021-02-13 Gabe Blackscons: Work around a scons bug when calling TryCompile.
2021-02-13 Gabe Blackarch-x86: Use popCount from bitfields.hh.
2021-02-13 Gabe Blackarch: Stop including unnecessary FP headers.
2021-02-12 Tiago Mückmem-ruby: intToTick helper
2021-02-12 Tiago Mückmem-ruby: add wakeup_port statement
2021-02-11 Tiago Mückmem-ruby: add andMask to WriteMask
2021-02-11 Tiago Mückpython: more readable Ruby dot topology
2021-02-11 Kyle Roartyarch-gcn3: Fix sign extension for branches with multipl...
2021-02-11 Gabe Blackscons: Simplify kvm architecture compatibility check.
2021-02-11 Gabe Blackscons: Merge redundant checks for the socket library.
2021-02-11 Gabe Blackscons: Simplify the check for protoc.
2021-02-11 Gabe Blackscons: Create a Configure checker for pkg-config.
2021-02-11 Gabe Blackscons: Simplify the check for hdf5 support.
2021-02-11 Gabe Blackscons: Simplify backtrace implementation detection.
2021-02-11 Gabe Blackscons: Simplify check for have_posix_clock.
2021-02-11 Gabe Blackscons: Move a displaced have_posix_clock check back...
2021-02-11 Gabe Blackscons: Use conf to determine if some flags are supported.
2021-02-11 Gabe Blackscons: In Check(Cxx|Link)Flag, only install the flag...
2021-02-11 Tiago Mückmem-ruby: fix Sequencer latency reporting
2021-02-11 Tiago Mückmem-ruby: fix functional reads in abstract ctrl
2021-02-11 Tiago Mückmem-ruby: fixes for masked writes
2021-02-11 Tiago Mückmem-ruby: warns on masked functional writes
2021-02-11 Giacomo Travagliniarch-arm: Fix CPTR_EL2 writes
2021-02-10 Hoa Nguyenmem: Initialize pendingWrites stat of NVMStats
2021-02-10 Gabe Blackscons: Pull Configure() to earlier in SConstruct so...
2021-02-10 Daniel R. Carvalhobase: Fix copyright of base/stats/SConscript
2021-02-10 Gabe Blackscons: Extract the gem5 specific Configure call to...
2021-02-10 Gabe Blackscons: Trim down a check for mac OS and arch setting...
2021-02-10 Gabe Blackscons: Remove "TIMEOUT" variable and checks.
2021-02-10 Gabe Blackscons: Update the Check(Cxx|Link)Flag checks to set...
2021-02-10 Gabe Blackscons: Remove partial linking.
2021-02-10 Gabe Blackcpu: Delete the empty, default off "nocpu".
2021-02-10 Giacomo Travaglinidev-arm: Add VRAM to VExpress_GEM5_Base
2021-02-10 Gabe Blackscons: Add support for debug info compression.
2021-02-10 Hoa Nguyencpu: Remove units from stats description
2021-02-10 Hoa Nguyenarch-riscv: Fixed the style of stats variable names...
2021-02-10 Hoa Nguyendev,dev-arm: Remove units from stats description
2021-02-10 Hoa Nguyenmem: Remove units from stats description
2021-02-10 Hoa Nguyenbase-stats: Print Units in Stats dump
2021-02-10 Hoa Nguyenmem: Change warmupCycle stat to warmupTick
2021-02-10 Hoa Nguyencpu: Add Units to cpu stats
2021-02-10 Hoa Nguyenlearning-gem5: Add units to stats
2021-02-10 Hoa Nguyenarch-arm,arch-riscv,arch-x86: Add units to stats
2021-02-10 Hoa Nguyendev,dev-arm: Add units to stats in /src/dev
2021-02-10 Hoa Nguyensim: Add units to src/sim
2021-02-10 Hoa Nguyenmem: Add Units to mem stats
2021-02-10 Hoa Nguyencpu,mem: Converting stats to supported units
2021-02-10 Hoa Nguyenmem: Fix/Improve stats in src/mem
2021-02-10 Hoa Nguyenbase-stats: Add Units to Stats
2021-02-10 Gabe Blackcpu: Track misc regs in vectors in the O3 CPU instructi...
2021-02-10 Gabe Blackcpu: Track flat register indices in the Minor CPU with...
2021-02-10 Gabe Blackcpu: Factor MaxInst(SrcDest)Regs out of the trace CPU.
2021-02-09 David Schallbase: Add XOR and modulo operator to ChannelAddr
2021-02-09 Gabe Blacksim: Get rid of the IsConforming type trait template.
2021-02-09 Gabe Blackarch,sim: Use VPtr<> instead of Addr in system call...
2021-02-08 Giacomo Travaglinidev-arm: Reduce boilerplate when read/writing to Pio...
2021-02-07 Daniel R. Carvalhodev: Fix register bank unit test in .debug
2021-02-07 Daniel R. Carvalhobase: Fix storage unit test in .fast
2021-02-06 Gabe Blacktests,base: Delete the SymbolTable::load method and...
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