soc.git
2021-02-17 Cesar StraussSetup SVSTATE, from the test settings, at the start
2021-02-16 Cesar StraussFix MSB0 issues for SVP64
2021-02-16 Tobias Platenmmureq handling
2021-02-16 Tobias Platendcache error handling
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-16 Luke Kenneth... ordering wrong on svstate in ISACaller
2021-02-16 Luke Kenneth... adapt botchify so it can be used for 31- or 15- etc...
2021-02-16 Luke Kenneth... add indicator to PowerDecoder2 when no outputs are...
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it...
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL
2021-02-15 Cesar StraussSimplify obtaining the PC from the register file
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Cesar StraussShow traces for the register numbers of the current...
2021-02-14 Cesar StraussFix width of the "extra" input on the Extra decoder
2021-02-14 Cesar StraussFix conversion to MSB0
2021-02-14 Cesar StraussRemove obsolete comment
2021-02-14 Luke Kenneth... add comments to TestIssuer
2021-02-14 Luke Kenneth... add srcstep onto Vectorised GPRs in PowerDecoder2
2021-02-14 Luke Kenneth... add TestRunner comments
2021-02-14 Luke Kenneth... add Regfiles comments
2021-02-14 Luke Kenneth... add SVSTATE reading to TestIssuer
2021-02-14 Luke Kenneth... add SVSTATE to CoreState
2021-02-14 Luke Kenneth... add extra FSM explanatory comments to TestIssuer
2021-02-13 Luke Kenneth... use function for getting instruction from 32/64 bit...
2021-02-13 Cesar StraussFetch and decode the SVP64 prefix
2021-02-13 Tobias PlatenOP_TLBIE must in be instr_is_priv
2021-02-13 Tobias Platenkeep commits to under 80 chars
2021-02-13 Cesar StraussCheck the PC value at the end of each instruction
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case
2021-02-13 Cesar StraussFix imports and whitespace
2021-02-13 Luke Kenneth... update svp64 unit test comments
2021-02-13 Tobias Platenforward microwatt mmu specific SPR: PID and PRTBL
2021-02-13 Luke Kenneth... add SVP64 TestIssuer separate unit test
2021-02-13 Luke Kenneth... split out TestRunner into separate module
2021-02-13 Cesar StraussFix SVP64 translator to yield the unaltered instruction
2021-02-12 Luke Kenneth... add one SVP64 ALU test case to get started
2021-02-12 Luke Kenneth... add SVSTATE to TestCase infrastructure for use in TestI...
2021-02-12 Luke Kenneth... add skip of instruction if SVSTATE.VL=0 in ISACaller
2021-02-12 Luke Kenneth... validate all registers to make sure no damage occurs...
2021-02-12 Luke Kenneth... add srcstep and correct PC-advancing during Sub-PC...
2021-02-12 Luke Kenneth... comments
2021-02-12 Luke Kenneth... add in SVSTATE.srcstep update, loop from 0 to VL-1
2021-02-12 Luke Kenneth... allow PC to update by 8 in SVP64 mode
2021-02-12 Luke Kenneth... fix setting of SVSTATE.VL and MVL
2021-02-12 Luke Kenneth... add in SVSTATE to ISACaller, not used, just passed in
2021-02-11 Luke Kenneth... comments in TestIssuer for SVP64PrefixDecoder
2021-02-10 Luke Kenneth... add svp64 reg decode detection to ISACaller output
2021-02-10 Luke Kenneth... starting to add SVP64 register EXTRA-read and isvec...
2021-02-10 Luke Kenneth... comment update
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore
2021-02-09 colepoirierfix erroneous removal of proof* from experiment/formal...
2021-02-07 colepoirieradd skeleton implementation of experiment/formal/proof_...
2021-02-07 colepoiriericache.py fix formatting
2021-02-07 colepoirierModify experiment/formal/.gitignore because was prevent...
2021-02-06 Cesar StraussFix whitespace
2021-02-06 Cesar StraussExtract the fetch FSM out from the main FSM
2021-02-05 Tobias Platenfix hanging simulation
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
2021-02-04 Tobias Platenupdate test_issuer_mmu_data_path.py to handle SPRs
2021-02-04 Tobias Platenpass SPR MicroOp to MMU function unit
2021-02-03 Luke Kenneth... nope - need it to be zero if not identified as svp64
2021-02-03 Luke Kenneth... actually no need to mux in the svp64_rm, just the id...
2021-02-03 Luke Kenneth... add SVP64PowerDecoder, extracts svp64 remap if correctl...
2021-02-01 Luke Kenneth... ISACaller, in svp64 mode, read the next 32 bits when...
2021-02-01 Tobias Platenextending the GTKWave document in test_issuer when...
2021-02-01 Luke Kenneth... sort out SelectableInt bit-ordering for identifying...
2021-02-01 Luke Kenneth... construct the assembly-code prefix and base v3.0B in...
2021-02-01 Cesar StraussAdd GTKWave document to test_issuer
2021-01-31 Cesar StraussFix loop test and enable it
2021-01-31 Luke Kenneth... start an ISACaller SVP64 unit test
2021-01-31 Luke Kenneth... test SVP64 major opcode, start checking if it is EXT001...
2021-01-31 Luke Kenneth... adjusting ISACaller unit test to use ISACaller.setup_one()
2021-01-31 Luke Kenneth... fix ISACaller unit test
2021-01-31 Tobias Platenfix two syntax errors in src/soc/decoder/isa/caller.py
2021-01-31 Luke Kenneth... SVP64 Remap Fields structures for ISACaller
2021-01-31 Luke Kenneth... remove sv_rm from PowerDecoder register decoders
2021-01-31 Luke Kenneth... add SVSTATE SPR sub-field accessor class to ISACaller
2021-01-31 Luke Kenneth... move SVP64 Extra reg decoding into main PowerDecoder...
2021-01-31 Luke Kenneth... update submodule
2021-01-30 Luke Kenneth... move CR in/out SVP64 EXTRA decoders into PowerDecoder
2021-01-30 Luke Kenneth... add SVP64 CR out extending to 7-bit in PowerDecoder2
2021-01-30 Luke Kenneth... add SVP64 CR EXTRA field-extension, from 3-bit to 7...
2021-01-30 Luke Kenneth... extend CR registers in Decode2ToExecute1Type to 7 bit
2021-01-30 Luke Kenneth... add SVP64CRExtra class to PowerDecoder2, turns 3-bit...
2021-01-30 Luke Kenneth... split out SVEXTRA field selection/decoding into separat...
2021-01-30 Luke Kenneth... whoops update PowerDecoder2 svp64 comments, reg sizes...
2021-01-30 Luke Kenneth... add SVP64 EXTRA decoding to RB, RC and RT (out) in...
2021-01-30 Luke Kenneth... add first SVP64 7-bit register context decoder to Power...
2021-01-29 Luke Kenneth... add SVP64RM record to PowerDecoder2
2021-01-29 Luke Kenneth... increase register number sizes from 5 to 7
2021-01-29 Luke Kenneth... syntax corrections, also size of maxvl was wrong
2021-01-29 Luke Kenneth... add SVP64 RM (Remap) Record
2021-01-29 Luke Kenneth... adjust SVP64RM class to output more PowerDecoder-friend...
2021-01-29 Luke Kenneth... adjust how register copy/setup is done in PowerDecoder2
2021-01-29 Luke Kenneth... add SV etype/ptype to power decoder
2021-01-29 Luke Kenneth... whoops syntax error. submodule update
2021-01-29 Luke Kenneth... start adding svp64 enums
2021-01-29 Luke Kenneth... use new svp64-augmented csv reader in PowerDecoder
2021-01-29 Luke Kenneth... whoops missed out "+" on explicit license listing
2021-01-28 Luke Kenneth... add SVSTATE to StateRegs
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