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soc.git
2021-03-18 Jacob Lifshaychange csv opcode field to require 0b... prefix and... commit | commitdiff | tree
2021-03-18 Jacob Lifshayupdate submodule commit | commitdiff | tree
2021-03-18 Jacob Lifshayforce opcode field to be always specified in binary... commit | commitdiff | tree
2021-03-18 Jacob Lifshayadd simplev.py to .gitignore commit | commitdiff | tree
2021-03-18 Jacob Lifshayupdate submodule commit | commitdiff | tree
2021-03-17 Luke Kenneth... correct comments commit | commitdiff | tree
2021-03-17 Luke Kenneth... re-enable SVP64 ISACaller predicate tests commit | commitdiff | tree
2021-03-17 Luke Kenneth... add ascii graphic for extsw svp64 operation commit | commitdiff | tree
2021-03-17 Luke Kenneth... add more explanatory comments commit | commitdiff | tree
2021-03-17 Luke Kenneth... add twin-predicated extsw SVP64 ISACaller unit test commit | commitdiff | tree
2021-03-17 Luke Kenneth... add SVP64 dststep incrementing in PowerDecoder2, Testis... commit | commitdiff | tree
2021-03-17 Luke Kenneth... add CR-based predication to ISACaller commit | commitdiff | tree
2021-03-17 Tobias Platencleanup raduxmmu._walk_tree commit | commitdiff | tree
2021-03-17 Tobias Platencreate iterative mmu lookup loop commit | commitdiff | tree
2021-03-17 Luke Kenneth... add SVP64 INT-style predication to ISACaller commit | commitdiff | tree
2021-03-17 Luke Kenneth... add predication SVP64 unit test commit | commitdiff | tree
2021-03-17 Luke Kenneth... add predication read ports (CR and INT) commit | commitdiff | tree
2021-03-17 Luke Kenneth... whoops shift has to be done at same bitwidth commit | commitdiff | tree
2021-03-17 Luke Kenneth... split out new_lookup function commit | commitdiff | tree
2021-03-17 Luke Kenneth... link up SVP64 RM Mode decoding into PowerDecoder2 commit | commitdiff | tree
2021-03-17 Luke Kenneth... add priv and mode to RADIXMMU commit | commitdiff | tree
2021-03-17 Luke Kenneth... add instr_fetch mode to ISACaller Mem and RADIXMMU commit | commitdiff | tree
2021-03-17 Luke Kenneth... whitespace commit | commitdiff | tree
2021-03-17 Luke Kenneth... add in SVP64 RM Mode decoder commit | commitdiff | tree
2021-03-16 Tobias Platenradixmmu: detect badtree commit | commitdiff | tree
2021-03-16 Tobias Platenadd valid, leaf to loop commit | commitdiff | tree
2021-03-16 Cesar StraussUse symbolic values for subfields and bits commit | commitdiff | tree
2021-03-16 Cesar StraussAdd subfield and bit definitions for the SVP64 RM mode... commit | commitdiff | tree
2021-03-16 Cesar StraussDefine and initialise the mode variable, to be used... commit | commitdiff | tree
2021-03-16 Cesar StraussRename class so it does not clash with the enum commit | commitdiff | tree
2021-03-15 Cesar StraussFix import commit | commitdiff | tree
2021-03-15 Tobias Platenadd rpte bitfields valid and leaf commit | commitdiff | tree
2021-03-14 Luke Kenneth... remove "sv." and replace with "sv" in all SVP64Asm commit | commitdiff | tree
2021-03-14 Luke Kenneth... remove "sv." and replace with "sv" in all SVP64Asm commit | commitdiff | tree
2021-03-14 Cesar StraussActivate the VL==0 loop with any SVP64 prefix whatsoever commit | commitdiff | tree
2021-03-13 Luke Kenneth... add setvl unit test assertions, add 2nd test commit | commitdiff | tree
2021-03-13 Luke Kenneth... get first revision setvl operational in ISACaller commit | commitdiff | tree
2021-03-13 Luke Kenneth... add setvl-to-long converter in SVP64Asm (sigh) commit | commitdiff | tree
2021-03-13 Luke Kenneth... add setvl unit test commit | commitdiff | tree
2021-03-13 Luke Kenneth... update submodule to include simplev setvl commit | commitdiff | tree
2021-03-13 Luke Kenneth... include SVSTATE in namespace, passing to ISACaller commit | commitdiff | tree
2021-03-12 Jacob Lifshayupdate submodule commit | commitdiff | tree
2021-03-12 Jacob Lifshayadd setvl to decoder commit | commitdiff | tree
2021-03-12 Jacob Lifshayautoformat code commit | commitdiff | tree
2021-03-12 Luke Kenneth... add OP_SETVL to MicrOp in power_enums.py commit | commitdiff | tree
2021-03-12 Luke Kenneth... add ability to set and distinguish RT=0 (RT_OR_ZERO... commit | commitdiff | tree
2021-03-12 Luke Kenneth... use PowerDecoder2.loop_continue instead of no_out_vec commit | commitdiff | tree
2021-03-12 Luke Kenneth... remove old code commit | commitdiff | tree
2021-03-12 Luke Kenneth... remove old code commit | commitdiff | tree
2021-03-12 Luke Kenneth... remove old code commit | commitdiff | tree
2021-03-12 Luke Kenneth... add more sophisticated checking of whether SVP64 loop... commit | commitdiff | tree
2021-03-12 Luke Kenneth... **FOR NOW** LD/ST relies on detection of twin-predicati... commit | commitdiff | tree
2021-03-12 Luke Kenneth... decoding of svp64 reg by name has to occur after immedi... commit | commitdiff | tree
2021-03-12 Jacob Lifshayadd forgotten PO (primary opcode) field to DecodeFields commit | commitdiff | tree
2021-03-11 Cesar StraussBring a few test cases from test_caller_64.py commit | commitdiff | tree
2021-03-11 Cesar StraussTest case for two successive SV instructions commit | commitdiff | tree
2021-03-11 Luke Kenneth... add link of RA_OR_ZERO SVP64 detection commit | commitdiff | tree
2021-03-11 Luke Kenneth... add detection of whether *full* 7-bit of RA is zero... commit | commitdiff | tree
2021-03-11 Luke Kenneth... add in SVP64 LD/ST basic test for ISACaller commit | commitdiff | tree
2021-03-11 Luke Kenneth... whoops sort out when svstate not active in ISACaller commit | commitdiff | tree
2021-03-11 Luke Kenneth... whoops PIDR is defined as 32-bits in SPRs.csv (and... commit | commitdiff | tree
2021-03-11 Luke Kenneth... add understanding of LDST immediates to SVP64ASM commit | commitdiff | tree
2021-03-11 Tobias Platenfix runtime error commit | commitdiff | tree
2021-03-10 Tobias Platenradix: reading first page table entry commit | commitdiff | tree
2021-03-10 Luke Kenneth... add walk_tree arguments it needs commit | commitdiff | tree
2021-03-09 Luke Kenneth... fix address must convert to SelectableInt commit | commitdiff | tree
2021-03-09 Luke Kenneth... call decode_ptre on address to obtain shift, mbits... commit | commitdiff | tree
2021-03-09 Tobias Platenwhitespace commit | commitdiff | tree
2021-03-09 Tobias PlatenRADIX: call self._walk_tree in ld and st commit | commitdiff | tree
2021-03-09 Luke Kenneth... debug radix mmu ISACaller commit | commitdiff | tree
2021-03-09 Tobias Platencomment out broken spr code commit | commitdiff | tree
2021-03-09 Tobias Platen_walk_tree: access sprs commit | commitdiff | tree
2021-03-09 Luke Kenneth... create first check_perms RADIX ISACaller function commit | commitdiff | tree
2021-03-09 Luke Kenneth... move Mem class out of ISACaller commit | commitdiff | tree
2021-03-09 Luke Kenneth... cleanup imports commit | commitdiff | tree
2021-03-09 Luke Kenneth... move ISACaller RADIX MMU class to separate module commit | commitdiff | tree
2021-03-09 Luke Kenneth... add pgtable and pte calculation to RADIX ISACaller commit | commitdiff | tree
2021-03-09 Cesar StraussEnable VL==0 vector instruction skip test case commit | commitdiff | tree
2021-03-09 Cesar StraussAdd some extra debug traces to the GTKWave document commit | commitdiff | tree
2021-03-09 Cesar StraussCreate a new signal for the Simulator to wait on commit | commitdiff | tree
2021-03-08 Luke Kenneth... start adding _get_prtable_addr commit | commitdiff | tree
2021-03-08 Luke Kenneth... actually make it possible to disable svp64 on commandli... commit | commitdiff | tree
2021-03-08 Luke Kenneth... add option in TestRunner to disable svp64 via commandli... commit | commitdiff | tree
2021-03-08 Luke Kenneth... add option to cut out SVP64 from PowerDecoder2 commit | commitdiff | tree
2021-03-08 Luke Kenneth... correct comments in sv.add rc=1 commit | commitdiff | tree
2021-03-08 Cesar StraussRemove the unused internal insn_done signal commit | commitdiff | tree
2021-03-08 Cesar StraussFix argument order to match function declaration commit | commitdiff | tree
2021-03-07 Cesar StraussFix missing NIA update on ISACaller commit | commitdiff | tree
2021-03-07 Luke Kenneth... whoops should be "make gitupdate" commit | commitdiff | tree
2021-03-07 Tobias PlatenRADIX: read SPRs commit | commitdiff | tree
2021-03-07 Tobias PlatenRADIX: implement memassign and call commit | commitdiff | tree
2021-03-07 Luke Kenneth... add SVSTATE read to DMI interface commit | commitdiff | tree
2021-03-07 Cesar StraussMerge WAIT_RESET into INSN_FETCH on the Issue FSM commit | commitdiff | tree
2021-03-07 Luke Kenneth... move DMI stuff to separate function in issuer.py commit | commitdiff | tree
2021-03-07 Luke Kenneth... update comments in issuer.py commit | commitdiff | tree
2021-03-07 Luke Kenneth... add Rc=1 SVP64 unit test to svp64_cases.py commit | commitdiff | tree
2021-03-07 Cesar StraussImplement the VL==0 loop commit | commitdiff | tree
2021-03-06 Cesar StraussAllow updating the PC and SVSTATE registers while stopped commit | commitdiff | tree
2021-03-06 Cesar StraussEnable the Simple-V loop test case commit | commitdiff | tree
2021-03-06 Cesar StraussBegin to implement the Simple-V loop commit | commitdiff | tree
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