| 2023-09-11 |
Jacob Lifshay | mark src/soc/experiment/test/test_compldst_multi.py... |
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| 2023-09-11 |
Jacob Lifshay | mark test_pi2ls.py as broken |
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| 2023-09-11 |
Jacob Lifshay | add cocotb to gitlab-ci |
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| 2023-09-11 |
Jacob Lifshay | add pytest-output-to-files's output dir to gitignore |
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| 2023-09-10 |
Jacob Lifshay | make CI work |
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| 2023-07-27 |
Andrey Miroshnikov | Makefile: Added rule for generating mw-compatible core... |
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| 2023-01-01 |
Cesar Strauss | Handle newer nMigen adding a "bench" hierarchy root... |
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| 2022-11-15 |
Cesar Strauss | Keep the valid signal from the formal engine ALU stable... |
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| 2022-10-28 |
Cesar Strauss | Check that exactly one ALU write is made, per instruction |
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| 2022-10-28 |
Cesar Strauss | Check cover and bmc in separate sub-tests |
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| 2022-10-26 |
Cesar Strauss | Reset req_l latch on system reset |
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| 2022-10-26 |
Cesar Strauss | Reset src_l latch on issue_i |
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| 2022-10-24 |
Luke Kenneth... | only NLnet sponsor |
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| 2022-10-16 |
Cesar Strauss | Move test to expose bug in MultiCompUnit |
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| 2022-10-12 |
Cesar Strauss | Check invariant for instruction operands |
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| 2022-10-12 |
Cesar Strauss | If the ALU is idle, do not assert valid |
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| 2022-10-09 |
Cesar Strauss | Count zero_a and imm_data.ok as masked read transactions |
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| 2022-10-09 |
Cesar Strauss | Don't issue while busy |
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| 2022-10-08 |
Cesar Strauss | Add count of masked reads |
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| 2022-10-08 |
Cesar Strauss | Add ALU read transaction counter |
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| 2022-10-08 |
Cesar Strauss | Add ALU write transaction counter |
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| 2022-10-08 |
Cesar Strauss | Add write transaction counter |
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| 2022-10-05 |
Cesar Strauss | Fix duplicate line (copy & paste error) |
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| 2022-10-01 |
Cesar Strauss | Add counter for operand reads |
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| 2022-10-01 |
Cesar Strauss | Avoid toggling go_i when rel_o is low |
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| 2022-10-01 |
Cesar Strauss | Leave shadow / die proof for last |
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| 2022-10-01 |
Cesar Strauss | Start of formal proof of MultiCompUnit |
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| 2022-08-16 |
Jacob Lifshay | change goldschmidt_div_sqrt to use nmutil.plain_data... |
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| 2022-08-14 |
Luke Kenneth... | grr not a yield function |
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| 2022-08-14 |
Luke Kenneth... | add get_fpregs stub function to HDLstate |
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| 2022-07-06 |
Luke Kenneth... | update pinmux submodule, rename to "fabric" |
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| 2022-07-06 |
Luke Kenneth... | add fabric compatibility mode |
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| 2022-07-05 |
Luke Kenneth... | MulOutputData was only 64-bit output not 128-bit |
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| 2022-07-04 |
Luke Kenneth... | add signal for resetting trap internal state (kaivb... |
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| 2022-07-04 |
Luke Kenneth... | set msr_o.data not msr_o Record in trap main_stage.py |
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| 2022-06-26 |
Luke Kenneth... | adapt TRAP function in main state pipeline to put KAIVB |
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| 2022-06-26 |
Luke Kenneth... | store KAIVB SPR 850 in TRAP Pipeline |
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| 2022-06-26 |
Luke Kenneth... | reduce icache/dcache TLB sizes |
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| 2022-06-26 |
Luke Kenneth... | update trap test_pipe_caller.py to use up-to-date test... |
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| 2022-06-26 |
Luke Kenneth... | missing module argument to TestRunner execute |
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| 2022-06-26 |
Luke Kenneth... | convert trap test_pipe_caller.py to consistent format |
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| 2022-05-23 |
Andrey Miroshnikov | Change usage of WB sel for individual control |
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| 2022-05-01 |
Luke Kenneth... | split out front of div into separate stage, still too... |
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| 2022-04-30 |
Luke Kenneth... | add missing module |
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| 2022-04-30 |
Luke Kenneth... | split off CR0/XER production in DIV Function Unit into... |
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| 2022-04-30 |
Luke Kenneth... | clear out DEC in core.cur_state.dec due to spurious... |
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| 2022-04-30 |
Cesar Strauss | Implement transparent read port option on the XOR wrapp... |
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| 2022-04-29 |
Jacob Lifshay | fix waay-too-precise error requirements |
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| 2022-04-29 |
Luke Kenneth... | add option to set small cache sizes in |
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| 2022-04-29 |
Jacob Lifshay | add comment |
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| 2022-04-29 |
Jacob Lifshay | fix so HDL works for 5, 8, 16, 32, and 64-bits. |
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| 2022-04-29 |
Jacob Lifshay | HDL works for io_width=5 |
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| 2022-04-28 |
Cesar Strauss | Test simultaneous transparent reads and partial writes |
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| 2022-04-28 |
Jacob Lifshay | add docs for clz |
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| 2022-04-28 |
Jacob Lifshay | add WIP HDL version of goldschmidt division -- it's... |
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| 2022-04-28 |
Luke Kenneth... | notes added to setup.py - absolute paranoia is needed on |
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| 2022-04-28 |
Jacob Lifshay | move GoldschmidtDivState |
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| 2022-04-28 |
Jacob Lifshay | add FIXME comments |
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| 2022-04-28 |
Jacob Lifshay | add the goldschmidt sqrt/rsqrt algorithm, still need... |
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| 2022-04-27 |
Jacob Lifshay | switch cached-property dependency to using libre-soc... |
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| 2022-04-27 |
Jacob Lifshay | improved goldschmidt division algorithm parameter optim... |
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| 2022-04-27 |
Jacob Lifshay | split out non-derived params into separate class withou... |
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| 2022-04-27 |
Jacob Lifshay | split out n_hat as separate property |
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| 2022-04-27 |
Jacob Lifshay | add default_cost_fn |
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| 2022-04-27 |
Jacob Lifshay | move GoldschmidtDivParams.get to bottom of class |
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| 2022-04-27 |
Jacob Lifshay | rename _goldschmidt_div_ops to GoldschmidtDivState... |
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| 2022-04-26 |
Jacob Lifshay | goldschmidt division works! still needs better paramete... |
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| 2022-04-26 |
Jacob Lifshay | fix goofed __init__.py file name |
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| 2022-04-25 |
Jacob Lifshay | working on goldschmidt_div_sqrt.py |
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| 2022-04-25 |
Jacob Lifshay | add cached_property dependency |
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| 2022-04-23 |
Jacob Lifshay | working on goldschmidt division algorithm |
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| 2022-04-22 |
Luke Kenneth... | whitespace |
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| 2022-04-22 |
Jacob Lifshay | add WIP goldschmidt division algorithm |
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| 2022-04-17 |
Cesar Strauss | Implement a 1W/1R register file, XOR style |
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| 2022-04-17 |
Cesar Strauss | Formal proof of pseudo 1W/2R SRAM |
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| 2022-04-17 |
Cesar Strauss | Add transparent option for the full read port |
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| 2022-04-17 |
Cesar Strauss | Implement a pseudo 1W/2R memory |
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| 2022-04-16 |
Luke Kenneth... | reduce dcache/icache number of ways, to fit into ECP5... |
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| 2022-04-16 |
Tobias Platen | part two of issuer_fix: read pspec.microwatt_old and... |
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| 2022-04-16 |
Cesar Strauss | Check non-transparent 1W/1R SRAM wrapper |
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| 2022-04-16 |
Cesar Strauss | Enable read port for non-transparent memories |
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| 2022-04-16 |
Tobias Platen | Merge ssh://git.libre-riscv.org:922/soc |
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| 2022-04-16 |
Tobias Platen | part one of issuer_fix: add parameter to issuer_verilog.py |
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| 2022-04-16 |
Cesar Strauss | Add port declarations to the SRAM wrappers |
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| 2022-04-16 |
Cesar Strauss | Change write lane signal from one-hot to binary |
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| 2022-04-16 |
Luke Kenneth... | whoops, WBASyncBridge ack signal not wired up! |
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| 2022-04-16 |
Luke Kenneth... | select width is data_width // data granularity. |
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| 2022-04-16 |
Cesar Strauss | Synchronize LVT state, completing the induction proof |
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| 2022-04-16 |
Cesar Strauss | Sync proof state with downstream memories |
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| 2022-04-16 |
Luke Kenneth... | put the old microwatt compatibility back |
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| 2022-04-16 |
Luke Kenneth... | blegh. |
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| 2022-04-15 |
Cesar Strauss | Complete moving the induction support into the DUT |
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| 2022-04-15 |
Cesar Strauss | Fix incorrect signal widths |
commit | commitdiff | tree |
| 2022-04-15 |
Cesar Strauss | Move part of formal proof to the implementation |
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| 2022-04-14 |
Luke Kenneth... | add option Spec to XICS ICP/ICS to be able to activate... |
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| 2022-04-14 |
Luke Kenneth... | move IRQLine out because that makes soc dependent on... |
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| 2022-04-14 |
Luke Kenneth... | 80 char limit, remove creation of stall from ack/cyc... |
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| 2022-04-14 |
Raptor Engineering... | wb_async: Allow different feature fields for master... |
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| 2022-04-14 |
Raptor Engineering... | Add separate memory clock register to SYSCON |
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| 2022-04-12 |
Tobias Platen | issuer.py: add microwatt_old and microwatt_debug options |
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projects / soc.git / shortlog