| 2020-08-15 | Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi... | commit | commitdiff | tree | 
| 2020-08-15 | Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi... | commit | commitdiff | tree | 
| 2020-08-15 | Luke Kenneth... | rather big change to interaction between regfile and... | commit | commitdiff | tree | 
| 2020-08-15 | Luke Kenneth... | clear compalu data latch always on issue | commit | commitdiff | tree | 
| 2020-08-15 | Cesar Strauss | Demonstrates string traces | commit | commitdiff | tree | 
| 2020-08-15 | Cesar Strauss | Demonstrates adding extra debug signals traces to the... | commit | commitdiff | tree | 
| 2020-08-15 | Cesar Strauss | Demonstrates creating stylish GTKWave "save" files... | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | remove latchregister, use sync to capture compunit... | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | ha! "state" (pc, msr) not properly passed to core | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | drop in insn_state synchronously in issuer, at same... | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | submodule update | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | hrfid unit test sets up HSRR0 and HSRR1 | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | bad hack to get HSRR0/1 to be "same" as SRR0/1 | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | bug in isa parser not recognising MSR as declared variable | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | hack to get hrfid not to alter msr 51 | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | stop trying to read swap files | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | sync on alu results in compalu | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | update submodule, add hrfid | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | update submodule, add hrfid | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | finally, fix decoder combinatorial loop | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | fix test_compunit.py after moving decoder rdflags function | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | add hrfid unit test | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | sync up the core decode-execute state, | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | move instruction decoder out of core | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | move regspec / rdflag decoding functions out of PowerDe... | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | sort out instruction stop/cancel when adding a new... | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | put multi-ports back (for read) on int and fast regfiles | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | reduce decoder pathways when exception occurs | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | divide shiftrot pipeline into 2 (simple last) | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | divide alu pipeline into 2 (simple last) | commit | commitdiff | tree | 
| 2020-08-14 | Luke Kenneth... | divide logical pipe into 2 (simple phase last) | commit | commitdiff | tree | 
| 2020-08-14 | Jacob Lifshay | running the simulator works! | commit | commitdiff | tree | 
| 2020-08-13 | Jacob Lifshay | add --cpu=libresoc to Makefile | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | fix dmi reg read | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | code-shuffle | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | remove use of latchregigister, replace with sync on... | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | sync on pc writing when changed | commit | commitdiff | tree | 
| 2020-08-13 | Cole Poirier | dcache.py add initial imports | commit | commitdiff | tree | 
| 2020-08-13 | Cole Poirier | mem_types.py add more types from common.vhdl | commit | commitdiff | tree | 
| 2020-08-13 | Cole Poirier | move memory related types from mmu.py into new file... | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | sync on reset in compalu | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | add forwarding-bus mode to Regfile Memory (and disable it) | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | sync on port interface address in ld/st compunit, and... | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | another sync to cut latency | commit | commitdiff | tree | 
| 2020-08-13 | Cole Poirier | Initial commit of translation of microwatt dcache.vhdl... | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | remove latchregister, sync src oper_i into MultiCompUnit | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | minor tidyup on alu compunit: | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | plenty of time to wait for operand, so use "sync" in... | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | sigh.  convert Fast regfile to binary | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | sync on read of regfile ports | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | sigh.  convert INT regfile to binary addressing | commit | commitdiff | tree | 
| 2020-08-13 | Luke Kenneth... | create a RegFileMem class that uses Memory | commit | commitdiff | tree | 
| 2020-08-12 | Jacob Lifshay | add run_sim to Makefile | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | mmu.py add skeleton sim and test functions from regfile... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | Delete unnecessary mmu dir, move mmu.py out of mmu... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | Revert "Remove mmu dir and associated mmu/test/ dir... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | Remove mmu dir and associated mmu/test/ dir | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | Remove rst signals, fix len of hex Consts, fix variable... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | Create dir experiment/mmu then mmu/test with skeleton... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | mmu.py add RecordObject classes from common.vhdl input... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | mmu.py remove TODOs for vhdl (others => '0') as they... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | mmu.py fix or(block of logic) to be (block of logic... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | mmu.py fix length of hex const https://bugs.libre-soc... | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | mmu.py remove class AddrShifter | commit | commitdiff | tree | 
| 2020-08-12 | Cole Poirier | Fix typo in mmu.py | commit | commitdiff | tree | 
| 2020-08-11 | Cole Poirier | mmu.py fix formatting, use Cat() where '&' in mmu.vhdl | commit | commitdiff | tree | 
| 2020-08-11 | Tobias Platen | initial version of L0CacheBuffer2 | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | sigh, remove yet another int regfile read port | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | massive reduction in gate count by using alternative... | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | reduce regfile port usage for INT and FAST | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | prepare write ports to be shared | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | move write regfile picker creation to new function | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | reduce regfile ports by creating separate STATE regfile | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | whoops fix change of variable (state) msr/pc | commit | commitdiff | tree | 
| 2020-08-11 | Luke Kenneth... | reducing regfile port usage by sharing read ports | commit | commitdiff | tree | 
| 2020-08-10 | Samuel A. Falvo II | WIP!!  Make MUL pipeline proof run again. | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | Fix typo in mmu.py | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | Fix typo mmu.py | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | Global search and replace (^, |), fixes bug 450 comment... | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | fix bug 450 comments 8,9,10 | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | Fix bug 450 comment 7 | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | mmu.py add line I forgot to translate from mmu.vhdl | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | commit | commitdiff | tree | 
| 2020-08-10 | Cole Poirier | mmu.vhdl translation to mmu.py 95 percent complete | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | stop combinatorial loop in pi2ls | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | write pulse in issuer | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | fix combinatorial loop in ldst compunit | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | use rising edge detection on st go_i/rel_o | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | add logical test issuer case | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | get rid of MSR read combinatorial loop | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | delay go_st by one cycle, break combinatorial loop | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | divwo case makes test_issuer stay busy! | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | add extra divwo regression test | commit | commitdiff | tree | 
| 2020-08-09 | Luke Kenneth... | compalu combinatorial loop detected | commit | commitdiff | tree | 
| 2020-08-08 | Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | commit | commitdiff | tree | 
| 2020-08-08 | Cole Poirier | Update test case_mulli | commit | commitdiff | tree | 
| 2020-08-08 | Tobias Platen | addr_split.py: shift bytes not bits | commit | commitdiff | tree | 
| 2020-08-07 | Cole Poirier | Update test case_mulli | commit | commitdiff | tree | 
| 2020-08-07 | Cole Poirier | Update test case_mulli, I think it now works correctly | commit | commitdiff | tree | 
| 2020-08-07 | Cole Poirier | Update mulli to try to use immediates not registers | commit | commitdiff | tree | 
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