soc.git
2020-05-13 Michael NolanAdd test for random rlcd(l/r) instructions
2020-05-13 Michael NolanFix bug in rotator preventing use of 64 bit rlcl/r
2020-05-13 Michael NolanUpdate to latest wiki version
2020-05-13 Luke Kenneth... add TODO placeholders for popcount and parity
2020-05-13 Luke Kenneth... minor tidyup
2020-05-13 Luke Kenneth... comments on ALU pipeline
2020-05-13 Luke Kenneth... update comment on Logical pipeline
2020-05-13 Luke Kenneth... remove Logical operations from ALU pipeline
2020-05-13 Luke Kenneth... split out Logical operations into separate pipeline
2020-05-13 Luke Kenneth... comments (and whitespace
2020-05-13 Michael NolanFix too wide bitfield being selected for opcode 30
2020-05-13 Michael NolanFix weirdness with rldicl and friends in test_caller.py
2020-05-13 Michael NolanAdd support for OP_EXTS
2020-05-13 Luke Kenneth... restore field decoders (works with BE/LE) in rotator
2020-05-13 Luke Kenneth... minor cleanup of shift_rot main_stage
2020-05-13 Michael NolanAdd missing input stage and pipe_data
2020-05-13 Luke Kenneth... simplift right_mask and left_mask rotator sub-functions...
2020-05-13 Michael NolanFix bug with ROTL32 helper
2020-05-13 Michael NolanSomewhat working now?
2020-05-13 Michael NolanIntegrate rotator.py into shift_rot unit
2020-05-13 Michael NolanUpdate cmp test in test_caller.py
2020-05-13 Michael NolanAdd assertions to ALU and shift_rot test that the instr...
2020-05-13 Michael NolanAdd SHIFT_ROT FU
2020-05-13 Michael NolanModify alu test to put reg1 *OR* reg3 into alu input A
2020-05-13 Michael NolanUpdate TODO
2020-05-13 Luke Kenneth... remove operand c from ALU in/out
2020-05-12 Luke Kenneth... temporary reorg of reg/immediate reading
2020-05-12 Luke Kenneth... add 3rd register input to ALUInputData
2020-05-12 Luke Kenneth... connect LDSTMulti to 6600 Scoreboard
2020-05-12 Luke Kenneth... when doing LD-immediate only acknowledge register 1...
2020-05-12 Michael NolanAdd new shift_rot FU for shifts and rotates
2020-05-12 Michael NolanRemove rotates and shifts from alu
2020-05-11 Michael NolanMassively spead up test_pipe_caller.py
2020-05-11 Michael NolanRevert "Greatly speed up test_pipe_caller.py"
2020-05-11 Michael NolanGreatly speed up test_pipe_caller.py
2020-05-11 Luke Kenneth... comments from discussion
2020-05-11 Michael NolanReverse bit order for cr0 in proof
2020-05-11 Michael NolanCheck output of cr0 from alu
2020-05-11 Michael NolanAdd carry in input to alu testbench
2020-05-11 Michael NolanAdd ability to specify initial state for SPRs
2020-05-11 Michael NolanFix proof_input_stage.py
2020-05-11 Michael NolanFix rlwimi by reordering the inputs *again*
2020-05-11 Michael NolanRe-enable rlwinm test
2020-05-11 Michael NolanCheck write register number too
2020-05-11 Michael NolanReorder the register reads so the field in read_reg2...
2020-05-11 Michael NolanHave test_pipe_caller actually read from the registers...
2020-05-11 Michael NolanActually implement rlwimi
2020-05-11 Luke Kenneth... comment input signals
2020-05-11 Luke Kenneth... cleanup rotator.py
2020-05-11 Luke Kenneth... add docstring, missing return module
2020-05-11 Luke Kenneth... start cleanup of rotator.py, Cat order is inverted
2020-05-11 Luke Kenneth... convert microwatt rotator to nmigen (first draft)
2020-05-10 Michael NolanAdd test for rlwnm
2020-05-10 Michael NolanImplement rlwimi as well
2020-05-10 Michael NolanImplement rlwinm in alu
2020-05-10 Michael NolanAdd test for rlwinm
2020-05-10 Michael NolanReduce BMC depth on proof_main_stage.py
2020-05-10 Luke Kenneth... use temporary python vars rather than copy signals...
2020-05-09 Michael NolanAdd shift left and shift right to main stage proof
2020-05-09 Luke Kenneth... sigh ton of syntax errors
2020-05-09 Luke Kenneth... bit of reorg, trick on add - put carry in into the LSB
2020-05-09 Luke Kenneth... comment output stage
2020-05-09 Luke Kenneth... comment maskgen
2020-05-09 Michael NolanHandle algebraic shifts too
2020-05-09 Michael NolanImplement logical shift right
2020-05-09 Michael NolanAdd support for sld
2020-05-09 Michael NolanChange shift left to be implemented with rotate and...
2020-05-09 Michael NolanAdd mask generator for shift class instructions
2020-05-09 Michael NolanAdd shift left opcode to main_stage
2020-05-09 Michael NolanFix broken mask when x == y
2020-05-09 Michael NolanAdd right shift test to test_caller.py
2020-05-09 Michael NolanAdd shift test to test_caller, fix fixedshift being...
2020-05-09 Michael NolanFix helpers.py not playing nicely with selectableInts
2020-05-09 Michael NolanAdd reversed add and subtract, as well as lshift and...
2020-05-09 Luke Kenneth... comment where ALUIntermediateData to go
2020-05-09 Luke Kenneth... TODO on AluIntermediateData
2020-05-09 Luke Kenneth... missing sticky-overflow pass-through from middle stage
2020-05-09 Luke Kenneth... pass through sticky-overflow
2020-05-09 Luke Kenneth... remove unneeded class
2020-05-09 Luke Kenneth... clarifying comments
2020-05-09 Michael NolanMinor cleanup
2020-05-09 Luke Kenneth... preliminary test for LD/ST "update" mode working
2020-05-09 Luke Kenneth... document PowerOp
2020-05-08 Luke Kenneth... add comments
2020-05-08 Luke Kenneth... add ALUFirstInputData
2020-05-08 Luke Kenneth... send address to memory only for one cycle and acknowled...
2020-05-08 Luke Kenneth... experimenting
2020-05-08 Luke Kenneth... working indexed version of LD/ST CompUnit
2020-05-08 Luke Kenneth... hmmm i think LD/ST Comp Unit might actually be working...
2020-05-08 Michael NolanOops, forgot pipeline.py
2020-05-08 Michael NolanAdd tests for immediates, add subf to tests
2020-05-08 Michael NolanAdd comments about the purpose of each alu stage
2020-05-08 Michael NolanAdd test for alu against simulator
2020-05-08 Michael NolanAdd assertions for output stage cr0
2020-05-08 Michael NolanAdd output stage
2020-05-08 Michael NolanAdd and or and xor to main_stage
2020-05-08 Michael NolanAdd carry in and out
2020-05-08 Michael NolanHave input_stage set the b operand to imm_data if it...
2020-05-08 Michael NolanAdd extra bits (carry, overflow, etc) to input and...
2020-05-08 Michael NolanBegin adding main ALU stage
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