soclayout.git
2021-06-09 Jean-Paul ChaputRemove files that are now copied from other locations.
2021-06-08 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-06-08 Jean-Paul ChaputAdpapt e9/TSMC doDesign to the new size of the SRAMs...
2021-06-06 Luke Kenneth... argh, nsxlib cannot cope with 3 clocks!
2021-06-05 Luke Kenneth... add vss/vdd as pins, gets the net into the VST
2021-06-05 Luke Kenneth... set power type in fake pll vdd/vss
2021-06-05 Luke Kenneth... whoops, fake pll/mem need vss/vdd
2021-06-05 Luke Kenneth... whoops naming pads different from nets is important
2021-06-05 Luke Kenneth... sigh trying to find the right clock line
2021-06-05 Luke Kenneth... more comments
2021-06-05 Luke Kenneth... comment about por_clk
2021-06-05 Luke Kenneth... correct clock name for H-Tree in ls180
2021-06-05 Luke Kenneth... sort out clock names in experiments10_verilog
2021-06-05 Luke Kenneth... add coresync_clk to list of HTree
2021-06-05 Luke Kenneth... add dummy pll to experiments10_verilog
2021-06-05 Luke Kenneth... set various clocks to use H-Tree
2021-06-05 Luke Kenneth... add dummy (fake) PLL to experiments10_verilog for testing
2021-06-04 Jean-Paul ChaputUpdated experiments12 for the latest Coriolis.
2021-06-04 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-06-04 Jean-Paul ChaputUpdated configuration suited for experiment9/tsmc_c018.
2021-06-03 Luke Kenneth... add 4ksram recon script in tsmc_c018 as well
2021-06-03 Luke Kenneth... add build_full_4ksram_recon.sh to copy over Staf re...
2021-06-03 Luke Kenneth... rename sys_clk to sys_clk_0 and rename ref_clk to sys_clk
2021-06-03 Staf VerhaegenReroute clk so PLL output clock is used as sys_clk.
2021-06-03 Staf VerhaegenDuplicate file before patching for clock rerouting.
2021-06-03 Luke Kenneth... rename ref in fake-pll to ref_v
2021-06-03 Luke Kenneth... update libresoc.v to use sys_clk for main core
2021-06-03 Luke Kenneth... change ref to ref_v in PLL (keyword)
2021-05-27 Luke Kenneth... set other nets to input in fake 4k SRAM cell
2021-05-27 Luke Kenneth... add TODO into tsmc_c018 coriolis2 settings.py
2021-05-27 Luke Kenneth... update libresoc.v
2021-05-27 Luke Kenneth... set fake-mem LibreSOCMem output q as a Net Output
2021-05-27 Luke Kenneth... set fake PLL Master Cell directions explicitly
2021-05-26 Luke Kenneth... clk_sel_i in TestIssuer was one bit not 2
2021-05-26 Luke Kenneth... remove sram4k wb err (unused anyway)
2021-05-26 Luke Kenneth... appears to be missing libresoc from NETLISTS in Makefile
2021-05-25 Luke Kenneth... attempt better grid alignment for fake cells
2021-05-25 Luke Kenneth... change cell sizes to grid layout (?)
2021-05-25 Luke Kenneth... increase not-connected pads by one
2021-05-25 Luke Kenneth... add fake pll symlink
2021-05-25 Luke Kenneth... rename pll out signal to out_v in "fake" pll cell
2021-05-25 Luke Kenneth... rename PLL out to out_v in test_issuer
2021-05-25 Luke Kenneth... rename pll blackbox out to out_v
2021-05-24 Luke Kenneth... disappearing signal from pll, attempt to get it back
2021-05-24 Luke Kenneth... remove "*" net from fake-pll cell, it ends up in the...
2021-05-24 Luke Kenneth... round to 0.135 cell grid?
2021-05-24 Luke Kenneth... rename cell to "real_pll" to avoid conflict with cell...
2021-05-24 Luke Kenneth... add dummy/fake/ghost PLL blackbox cell
2021-05-22 Luke Kenneth... rename PLL pad names
2021-05-22 Luke Kenneth... correct PLL names
2021-05-22 Luke Kenneth... re-add 4k sram
2021-05-22 Luke Kenneth... annoying rename of pll analog pin
2021-05-22 Luke Kenneth... manually rename ls180sram4k module to ls180
2021-05-22 Luke Kenneth... submodule update
2021-05-22 Luke Kenneth... update PLL to use submodule Instance
2021-04-30 Luke Kenneth... do an SRAM search by looking for matching along the...
2021-04-30 Luke Kenneth... 4k sram build
2021-04-30 Luke Kenneth... use "make view" not "make vst"
2021-04-30 Luke Kenneth... add fake LibreSOCMem library to freepdk_c4m45
2021-04-30 Luke Kenneth... add symlink to "fake" LibreSOCMem
2021-04-30 Luke Kenneth... enabling experiments9 new LibreSOCMem fake blackbox...
2021-04-30 Luke Kenneth... using renamed (single) spblock_512w64b8w
2021-04-30 Luke Kenneth... using new single spblock_512xxx in experiments9
2021-04-30 Luke Kenneth... add complete series of pins onto fake SRAM
2021-04-28 Luke Kenneth... first experiment creating a LibreSOCMem library with...
2021-04-28 Luke Kenneth... create function which pre-creates the blackbox cells
2021-04-28 Luke Kenneth... name everything back to spblock_512w64b8w now that...
2021-04-28 Luke Kenneth... rename spblock modules to just straight spblock_512w64b...
2021-04-28 Luke Kenneth... also add createSRAMblocks to freepdk_c4m45
2021-04-28 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-04-28 Jean-Paul ChaputManagement of SRAMs block at Coriolis devel.
2021-04-28 Luke Kenneth... add vbe spblock models to non_generated and build scripts
2021-04-28 Luke Kenneth... shrinking regfile sizes some more
2021-04-27 Luke Kenneth... add blackbox attribute to spblock512*.v
2021-04-27 Luke Kenneth... also add blackboxes spblock512* etc.
2021-04-27 Luke Kenneth... add copying over of spblock*.v and pll.v to build scripts
2021-04-25 Luke Kenneth... submodule update
2021-04-25 Jean-Paul ChaputCorrect setup for experiment9/freepdk_c4m45, restrict...
2021-04-24 Luke Kenneth... update submodule
2021-04-24 Luke Kenneth... cleanup mksyms.sh to include FreePDK_C4M45
2021-04-24 Luke Kenneth... add export of PDKMASTER_TOP to experiments9/freepdk_c4m45
2021-04-24 Luke Kenneth... correct relative link to FreePDK45_c4m45, use submodule
2021-04-24 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-04-24 Jean-Paul ChaputForgot to update experiments9 doDesign file for FreePDK 45.
2021-04-24 Jean-Paul ChaputKeep in synch with the latest Coriolis. SRAM models...
2021-04-24 Jean-Paul ChaputCorrect settings for experiment10_verilog & FreePDK45.
2021-04-22 Luke Kenneth... make placement of SRAMs optional, and PLL as well,...
2021-04-20 Luke Kenneth... manually comment out pll and sdcard pins
2021-04-19 Staf Verhaegenexperiments10_verilog/freepdk_c4m45: Add link for add.py.
2021-04-19 Staf VerhaegenTop layer -> metal6
2021-04-19 Staf Verhaegenexperiments9/freepdk_c4m45: Reduce core size.
2021-04-19 Luke Kenneth... add SPBlock512 instance generator
2021-04-19 Luke Kenneth... code-comments
2021-04-19 Luke Kenneth... add two SRAMs, document how to do more
2021-04-18 Luke Kenneth... argh, found the blackbox problem: yosys is "doing the...
2021-04-18 Luke Kenneth... try renaming spblock without the underscore
2021-04-18 Luke Kenneth... try changing layout of blackbox spblock_512w64b8w
2021-04-18 Luke Kenneth... experimenting with blackboxes
2021-04-18 Luke Kenneth... rename spblock_512w64b8w, and vco_test_ana for pll
2021-04-18 Luke Kenneth... rename blackboxes to lowercase, spblock_512w64b8w, pll
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