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soc.git
2020-08-07
Cole Poirier
Update mulli to try to use immediates not registers
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2020-08-06
Cole Poirier
Fix mmu.py formatting
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2020-08-06
Cole Poirier
Fix formatting
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2020-08-06
Cole Poirier
Initial commit of translation of microwatt mmu.vhdl...
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2020-08-06
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-06
Cole Poirier
Update test case_all_rb_close_to_ov
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2020-08-06
Cole Poirier
Update test case_all_rb_close_to_ov
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2020-08-06
Luke Kenneth...
fix LDST PortInterface FSM interaction
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2020-08-06
Luke Kenneth...
MULS on parameter b needed to check whether it was...
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2020-08-06
Cole Poirier
Add special test for case_mulli, apply autopep8
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2020-08-05
Cole Poirier
Add test case_all_rb_close_to_ov
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2020-08-05
Cole Poirier
Remove mulli from instrs in test case_all*, add TODO...
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2020-08-05
Cole Poirier
Add new test_values to tests case_all and case_all_rb_r...
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2020-08-05
Cole Poirier
Add second case_all test where rb is randint
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2020-08-05
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-08-05
Tobias Platen
undo changes that fix unit test, but do not solve anything
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2020-08-05
Luke Kenneth...
rename ibus/dbus (shorten)
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2020-08-05
Luke Kenneth...
clear sel on loadstore
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2020-08-05
Tobias Platen
fix LDSTSplitter
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2020-08-05
Cole Poirier
Remove madd* isns, added madd* isns test TODO
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2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-05
Luke Kenneth...
adding bus data width of 64 in litex sim doesnt work
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2020-08-05
Luke Kenneth...
add div test cases into test_issuer.py
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2020-08-05
Luke Kenneth...
add div FSM as default for test_issuer in verilog and...
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2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-05
Jacob Lifshay
Fixed div pipe with FSM
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2020-08-05
Cole Poirier
Fix pysim deprecation warning
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2020-08-05
Cole Poirier
Add case_all to MUL unit tests, remove duplicate test...
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2020-08-04
Luke Kenneth...
read/set pc outside of FSM so that DMI interface can...
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2020-08-04
Luke Kenneth...
swap over byte-reverse if/else in LDSTCompUnit
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2020-08-04
Luke Kenneth...
tracked down byte-reversal in LDST ISACaller and LDSTCo...
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2020-08-04
Luke Kenneth...
whitespace after autopep8 messed up
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2020-08-04
Luke Kenneth...
msr and pc moved to "state" in PowerDecode2
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2020-08-04
Luke Kenneth...
whoops must output NIA not PC to debug DMI query in...
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2020-08-04
Luke Kenneth...
allow instruction to run if initiated whilst "stopped...
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2020-08-04
Luke Kenneth...
cycle through INT regs, read and debug in litex sim
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2020-08-04
Luke Kenneth...
add DMI debug interface to libresoc litex sim
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2020-08-04
Luke Kenneth...
single-step and print out PC using DMI in litex sim
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2020-08-04
Luke Kenneth...
get litex sim to kick off a "STEP" via the DMI interfac...
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2020-08-04
Luke Kenneth...
connect up a DMI FSM to litex sim
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2020-08-04
Luke Kenneth...
more remove wildcard imports
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2020-08-04
Luke Kenneth...
do not use wildcard imports
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2020-08-04
Luke Kenneth...
adding litex sim experimentation.
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2020-08-04
Samuel A. Falvo II
Remove XXX; this seems done otherwise.
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2020-08-03
Luke Kenneth...
add quick demo/test of reading DMI reg 9
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2020-08-03
Luke Kenneth...
add extra port for debug read of int regs via DMI
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2020-08-03
Luke Kenneth...
pass state (MSR/PC) around between PowerDecode2, DMI...
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2020-08-03
Luke Kenneth...
https://bugs.libre-soc.org/show_bug.cgi?id=446
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2020-08-03
Luke Kenneth...
use new soc.config.state CoreState class in DMI and...
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2020-08-03
Tobias Platen
LDSTSplitter: report exception
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2020-08-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-08-03
Tobias Platen
TstDataMerger2
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2020-08-03
Luke Kenneth...
change over to DMI debug start/stop interface
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2020-08-03
Luke Kenneth...
move debug to record
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2020-08-03
Samuel A. Falvo II
WIP: check MB > ME and select mask appropriately
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2020-08-02
Luke Kenneth...
convert microwatt core_debug.vhdl to nmigen
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2020-08-02
Luke Kenneth...
add debug dir
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2020-08-01
Luke Kenneth...
add quick test of litex bios IMM64 macro
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2020-08-01
Luke Kenneth...
add rlwnm test showing that shift rot OP_RLC proof...
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2020-08-01
Luke Kenneth...
line-length / whitespace
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2020-08-01
Luke Kenneth...
expand out for-loop setting up input record subset
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2020-07-31
Luke Kenneth...
reorg DecodeB in power_decoder2.py to sign-extend immed...
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2020-07-31
Luke Kenneth...
add more instructions to litex trampoline test (not...
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2020-07-31
Luke Kenneth...
restrict external port list further in test_issuer
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2020-07-31
Luke Kenneth...
missed go_i/rel_o rename
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2020-07-31
Samuel A. Falvo II
WIP: more debugging signals for inspection
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2020-07-30
Samuel A. Falvo II
WIP: rlwinm/rlwnm/rlwimi-type proofs
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2020-07-30
Tobias Platen
begin work on TestCase for two DataMergers/Cache
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2020-07-30
Tobias Platen
add CacheRecord
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2020-07-30
Luke Kenneth...
core_start/stop/endian were inverted (output)
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2020-07-30
Luke Kenneth...
ha! have to explicitly specify the ports when writing...
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2020-07-30
Luke Kenneth...
add trampoline test from litex
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2020-07-30
Luke Kenneth...
set sel line in minerva instruction fetch
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2020-07-30
Luke Kenneth...
ha! found source of XICS test bug: wishbone stb was...
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2020-07-29
Luke Kenneth...
more exploratory testing of XICS, joining ICP and ICS...
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2020-07-29
Tobias Platen
modified LDSTSplitter to conform to PortInterface
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2020-07-29
Luke Kenneth...
forgot to rename ad/st in LDSTCompUnitRecord
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2020-07-29
Luke Kenneth...
bit of a big change: add prefixes "cu_" to all CompUnit...
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2020-07-29
Luke Kenneth...
start on test joining XICS ICS to ICP
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2020-07-29
Luke Kenneth...
tidyup XICS, identify (potential?) bug?
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2020-07-29
Luke Kenneth...
move CR test out of subtest indentation
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2020-07-29
Luke Kenneth...
move SHIFTROT test out of subtest indentation
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2020-07-29
Luke Kenneth...
move actual ALU test out of subTest indentation just...
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2020-07-29
Luke Kenneth...
whitespace
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2020-07-29
Jacob Lifshay
clean up branch test_pipe_caller
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2020-07-29
Jacob Lifshay
clean up alu test_pipe_caller
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2020-07-29
Jacob Lifshay
add __init__.py to all source directories
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2020-07-29
Jacob Lifshay
clean up some tests
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2020-07-29
Jacob Lifshay
format some tests
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2020-07-29
Jacob Lifshay
add code for skipping test cases
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2020-07-28
Jacob Lifshay
clean up div pipe tests to allow them to be run in...
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2020-07-28
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-28
Jacob Lifshay
fix test_pipe_ilang.py
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2020-07-28
Luke Kenneth...
use ctx.op compare (and muxid) in shiftrot proof
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2020-07-28
Jacob Lifshay
split out ilang tests
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2020-07-28
Jacob Lifshay
add more files to .gitignore
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2020-07-28
Jacob Lifshay
format code
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2020-07-28
Luke Kenneth...
add preliminary investigative test of XICS ICS
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2020-07-28
Luke Kenneth...
tidyup/comments in trap proof
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2020-07-27
Luke Kenneth...
add 2nd part of XICS interrupt interface
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