soc.git
2020-09-24 Cole Poiriericache.py add some missing lines from icache.vhdl,...
2020-09-24 Cole Poiriermem_types.py wb_types.py add name constructor to all...
2020-09-24 Cole Poiriericache.py fixed all errors that raised python exception...
2020-09-24 Cesar StraussFix whitespace, remove unused imports
2020-09-24 Luke Kenneth... brackets round imports looks cleaner?
2020-09-24 Luke Kenneth... add jtag c4m pins which gives us a way to connect IO...
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-23 Luke Kenneth... cs_n and cke in sdram need to match in length
2020-09-23 Luke Kenneth... change litex sdram pinouts to ASIC type
2020-09-23 Luke Kenneth... redo litex SDCard to send out data/cmd o/i/en pins
2020-09-23 Luke Kenneth... sort out GPIO with i/o/oe in ls180
2020-09-23 Luke Kenneth... add ls180 pinmap text file
2020-09-23 Luke Kenneth... attempt GPIO bi-directional
2020-09-23 Luke Kenneth... add I2C master to ls180
2020-09-22 Luke Kenneth... add 2 PWMs (quick, easy to do)
2020-09-22 Luke Kenneth... move dmi_sim to separate module
2020-09-22 Jacob Lifshayupdate submodule url
2020-09-22 Jacob LifshayRevert "disable pia in div tests"
2020-09-22 Luke Kenneth... add openocd.cfg experiment
2020-09-22 Luke Kenneth... create a JTAG platform and connect it up. jtagremote...
2020-09-22 Luke Kenneth... add jtagremote to litex sim, add new "variant" to core...
2020-09-22 Luke Kenneth... link litex ls180soc JTAG pads
2020-09-22 Luke Kenneth... add jtag wishbone and jtag ports to libresoc litex...
2020-09-22 Luke Kenneth... add jtag interface to issuer_verilog
2020-09-22 Luke Kenneth... add sys_rst to Clock Reset Generator
2020-09-22 Luke Kenneth... add JTAG IOpads and rename rst to sys_rst
2020-09-22 Luke Kenneth... add similar platforms to ls180.py
2020-09-22 Luke Kenneth... add JTAG bus module
2020-09-22 Luke Kenneth... split out dmi2jtag into own unit test
2020-09-22 Luke Kenneth... submodule update
2020-09-22 Cesar StraussPort soc.experiment.alu_fsm to the new way of invoking...
2020-09-22 Luke Kenneth... disable pia in div tests
2020-09-22 Luke Kenneth... add MMU (commented out)
2020-09-21 Luke Kenneth... add missing file
2020-09-21 Luke Kenneth... add quick wishbone jtag test
2020-09-21 Luke Kenneth... experiment set dmi msr read
2020-09-21 Luke Kenneth... add DMI JTAG test
2020-09-21 Luke Kenneth... add JTAG basic unit test
2020-09-21 Luke Kenneth... arg complete rewrite of JTAG2DMI, based it on staf...
2020-09-20 Cesar StraussAdd induction proof for the FSM Shifter
2020-09-20 Cesar StraussAdd bounded proof to FSM Shifter
2020-09-20 Cesar StraussLet the formal engine create some test cases for the...
2020-09-20 Luke Kenneth... resolve issues in async sim: must not drive async clock...
2020-09-20 Luke Kenneth... still experimenting with async FF sync
2020-09-20 Luke Kenneth... continuing async clock experimenting
2020-09-20 Luke Kenneth... add an async clock synchronizer experiment
2020-09-20 Luke Kenneth... first version code-morph on dmi2jtag
2020-09-19 Luke Kenneth... add pc_o not connected
2020-09-19 Luke Kenneth... set ROM to empty, set SRAM to tiny 0x200, get things...
2020-09-19 Cesar StraussRemove demonstration code
2020-09-19 Luke Kenneth... urk. wishbone slave devices declared incorrectly (I... semi_working_ecp5
2020-09-19 Luke Kenneth... disable internal RAM set SRAM to much smaller
2020-09-19 Luke Kenneth... shrink size of SRAM to 8k, move things around
2020-09-19 Luke Kenneth... add (disabled) tri-state GPIO
2020-09-19 Luke Kenneth... remove the gpio peripheral which was previously hard...
2020-09-19 Luke Kenneth... add 3x EINTs to ls180soc
2020-09-18 Luke Kenneth... add SPI, sdcard, preliminary GPIO to ls180 pinouts
2020-09-18 Luke Kenneth... argh got fed up trying to shoe-horn into sim.py
2020-09-18 Luke Kenneth... can remove unneeded overrides of Prev/Next Control
2020-09-17 Jacob Lifshayadd divwe regression test case
2020-09-17 Jacob Lifshayre-enable test case -- no longer goes into an infinite...
2020-09-17 Jacob Lifshayfix bug #492
2020-09-17 Jacob Lifshayreplace sim._state.timeline.now with sim._engine.now
2020-09-17 Luke Kenneth... add versa ecp5 fpga litex build script
2020-09-16 Cole Poiriercomplete first translation pass of dmi_dtm_xilinx.vhdl...
2020-09-16 Luke Kenneth... make a start on LS180 platform
2020-09-16 Cole Poirierinitial commit of JTAGToDMI debug interface translated...
2020-09-16 Cole Poirieradd template file/starting point (copy of litex/boards...
2020-09-15 Luke Kenneth... add back (totally confusing) accidentally-removed code...
2020-09-15 Luke Kenneth... instantiate MMU from AllFunctionUnits
2020-09-15 Luke Kenneth... do not need FAST regs in MMU
2020-09-15 Luke Kenneth... comment mmu test
2020-09-15 Luke Kenneth... add edge-triggering to dcache/mmu "valid"
2020-09-15 Luke Kenneth... add set MTSPR prtbl to mmu unit test
2020-09-15 Luke Kenneth... add OP_MFSPR to mmu
2020-09-15 Luke Kenneth... use convenience vars
2020-09-15 Luke Kenneth... add OP_TLBIE to mmu fsm
2020-09-15 Luke Kenneth... add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
2020-09-15 Luke Kenneth... add MMU MTSPR connection into FSM
2020-09-15 Luke Kenneth... add in MMU and DCache into MMU FSM
2020-09-15 Luke Kenneth... moved PLRU to nmutil
2020-09-15 Luke Kenneth... add mmu fsm
2020-09-15 Luke Kenneth... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth... remove more (confusing/spurious) types, should be in...
2020-09-15 Luke Kenneth... removed (confusing/spurious) types, should be in .pyi...
2020-09-15 Luke Kenneth... add MMU FunctionUnit
2020-09-15 Luke Kenneth... mmu uses RB, go with it
2020-09-15 Luke Kenneth... add OP_TLBIE
2020-09-15 Luke Kenneth... add mmu initial pipe_data.py
2020-09-15 Luke Kenneth... add extra "modes" to PortInterface
2020-09-15 Luke Kenneth... syntax error correction
2020-09-15 Luke Kenneth... add inline comments into icache.py
2020-09-14 Cole Poiriericache.py add missing funciton bodies, add missing...
2020-09-14 Luke Kenneth... increase TLB_NUM_WAYS to 4
2020-09-14 Luke Kenneth... vhdl conversion not really working for plru
2020-09-14 Luke Kenneth... add array signal names
2020-09-14 Luke Kenneth... rename plru input
2020-09-14 Luke Kenneth... rename plru input
2020-09-14 Luke Kenneth... reorg mmu lookup test so it is called twice
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