2021-05-09 |
Luke Kenneth... | add in alignment exception capture/reporting in LoadStore1 |
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2021-05-09 |
Luke Kenneth... | preference is to create a temp variable for comb and... |
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2021-05-09 |
Luke Kenneth... | add misalign flag to PortInterfaceBase |
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2021-05-08 |
Luke Kenneth... | LoadStore1 tidyup |
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2021-05-08 |
Luke Kenneth... | transferring more over to LoadStore FSM |
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2021-05-08 |
Luke Kenneth... | start putting state info into LoadStore1, slowly puttin... |
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2021-05-08 |
Luke Kenneth... | add LoadStore State enum |
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2021-05-08 |
Luke Kenneth... | add bugreport link to mmu |
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2021-05-07 |
Tobias Platen | fix 'sync' referenced before assignment in src/soc... |
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2021-05-07 |
Luke Kenneth... | start setting DSISR bits but commented out |
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2021-05-07 |
Luke Kenneth... | update comments and docstrings |
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2021-05-07 |
Luke Kenneth... | whoops, import error |
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2021-05-07 |
Luke Kenneth... | move LoadStore1 class to soc.fu.ldst.loadstore |
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2021-05-07 |
Luke Kenneth... | whoops was still copying output over in CommonOutputStage |
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2021-05-07 |
Luke Kenneth... | how we managed to get this far without noticing that... |
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2021-05-07 |
Luke Kenneth... | move dsisr and dar into LoadStore1 |
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2021-05-07 |
Luke Kenneth... | move zero-dest-pred in Common Output Stage to not copy... |
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2021-05-07 |
Luke Kenneth... | whoops setup of core.sv_pred_sm/dm not indented and... |
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2021-05-06 |
Luke Kenneth... | whoops disabled tests agaaaaain |
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2021-05-06 |
Luke Kenneth... | pass relevant predicate mask bits through to Decoders... |
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2021-05-06 |
Luke Kenneth... | add in predicate mask bit detection when zeroing is... |
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2021-05-06 |
Luke Kenneth... | pass SVP64 ReMap field through to core and then on... |
commit | commitdiff | tree |
2021-05-06 |
Luke Kenneth... | moved exts* SVP64 unit tests to a different location |
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2021-05-06 |
Jonathan Neuschäfer | .gitlab-ci.yml: Increase the build timeout |
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2021-05-06 |
Luke Kenneth... | argh someobe falsely stated in the README that LibreSOC... |
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2021-05-06 |
Luke Kenneth... | if zeroing is set, put zero into input or output as... |
commit | commitdiff | tree |
2021-05-05 |
Tobias Platen | fix bug in mmu/fsm.py |
commit | commitdiff | tree |
2021-05-05 |
Luke Kenneth... | simplify README.md so that it gets submitted to pypi |
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2021-05-05 |
Luke Kenneth... | mark long description type as markdown |
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2021-05-05 |
Luke Kenneth... | update NEWS.txt |
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2021-05-05 |
Luke Kenneth... | add libresoc-openpower-isa to setup.py dependencies |
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2021-05-05 |
Luke Kenneth... | put sv_input_record_layout onto CompOpSubsetBase after all |
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2021-05-05 |
Luke Kenneth... | whoops wrong signal name, set exc_happened |
commit | commitdiff | tree |
2021-05-05 |
Luke Kenneth... | add SVP64 RM fields to ALU input record |
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2021-05-04 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-05-04 |
Tobias Platen | implement MFSPR the same way as fu/spr/main_stage.py |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | remove minerva debug unit (not needed) |
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2021-05-04 |
Jonathan Neuschäfer | minerva tests: Don't import soc.minerva.csr |
commit | commitdiff | tree |
2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Silence pywriter harder |
commit | commitdiff | tree |
2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Trim log output |
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2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Fix invocation of pywriter |
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2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build power-instruction-analyzer |
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2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build c4m-jtag |
commit | commitdiff | tree |
2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Clone and build openpower-isa |
commit | commitdiff | tree |
2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Install Rust and cargo |
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2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Remove tags from nmigen-soc repo |
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2021-05-04 |
Jonathan Neuschäfer | .gitlab-ci.yml: Rewrite git://git.libre-riscv.org URLs... |
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2021-05-04 |
Luke Kenneth... | whoops disabled some test_issuer group tests |
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2021-05-04 |
Luke Kenneth... | add SVSTATE (SVSRR0) to TRAP pipeline |
commit | commitdiff | tree |
2021-05-04 |
Tobias Platen | upate dsisr and dar using sync |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | adding fast3 SPR to Trap pipeline and unit test |
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2021-05-04 |
Luke Kenneth... | new fast3 needs to be remapped to fast1 port in "reduce... |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | missed that soc.regfile.util has moved to openpower... |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | add SVSRR0 to FastRegsEnum |
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2021-05-04 |
Luke Kenneth... | add TODO comments and cross-reference to bug |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | note a way to see if an exception happened, in TestIssuer |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | add printout showing exception output from FUs |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | remove symlink |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | add links in README |
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2021-05-04 |
Luke Kenneth... | more rename of exception_o to exc_o, add convenience... |
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2021-05-04 |
Luke Kenneth... | wire in exc_o.happened into write-cancellation of LDSTC... |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | comments, and change name of LDSTCompUnit exception_o... |
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2021-05-04 |
Luke Kenneth... | remove exception from data on FUBaseData, explicitly... |
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2021-05-04 |
Luke Kenneth... | code-comments for LDSTCompUnit |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | add LDSTException class to LDSTOutputData |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | add option to add exception type to FUBaseData (pipe_data) |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | rename IntegerData to FUBaseData |
commit | commitdiff | tree |
2021-05-04 |
Luke Kenneth... | comment out nc (nocache), it seems to actually work |
commit | commitdiff | tree |
2021-05-03 |
Luke Kenneth... | MMU: get store to activate only when data is available... |
commit | commitdiff | tree |
2021-05-03 |
Luke Kenneth... | disable the cache for now, whilst testing read/write... |
commit | commitdiff | tree |
2021-05-02 |
Luke Kenneth... | use Const to define bit-length when comparing top nibbl... |
commit | commitdiff | tree |
2021-05-02 |
Luke Kenneth... | mmu FSM store in dcache: only put data onto d_in on... |
commit | commitdiff | tree |
2021-05-02 |
Luke Kenneth... | return d_out.valid instead of always "ok" in MMU FSM |
commit | commitdiff | tree |
2021-05-02 |
Luke Kenneth... | HACK WARNING: disable d-cache on hard-coded address... |
commit | commitdiff | tree |
2021-05-02 |
Luke Kenneth... | add nc argument to dcache load/store tests |
commit | commitdiff | tree |
2021-05-02 |
Luke Kenneth... | quick hack to SRAM test and to dcache to enable classic... |
commit | commitdiff | tree |
2021-05-02 |
Luke Kenneth... | adjust dependencies in setup.py |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | enable issuer_verilog.py to generate new MMU/DCache... |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | send a DMI RESET at the end of the test. |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | store data in microwatt dcache goes in one cycle AFTER... |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | dcache store test: data goes in one cycle AFTER valid... |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | only do dcache lookup for now |
commit | commitdiff | tree |
2021-05-01 |
Cesar Strauss | Add GTKWave documents to each DCache unit test |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | add LD/ST cases to MMU, which should all still work |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | add MMUTestCaseROM |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | whitespace |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | use new AllFunctionUnits.get_fu function |
commit | commitdiff | tree |
2021-05-01 |
Luke Kenneth... | use SPRreduced to match PowerDecoder2 |
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2021-05-01 |
Luke Kenneth... | missing self. |
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2021-05-01 |
Luke Kenneth... | resolve DriverConflict in TstL0CacheBuffer, really... |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | debug and stop on mmu test_pipe_caller.py |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | comments on dcache-to-mmu link |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | add a TestSRAM variant of LoadStore1, for being able... |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | add basic test_issuer_mmu.py |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | add option to use new mmu_cache_wb ConfigMemoryPortInte... |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | hook up dcache wb_in/out to PortInterfaceBase Wishbone... |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | sort out spblock 4k sram cell instance name to match... |
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2021-04-30 |
Luke Kenneth... | https://bugs.libre-soc.org/show_bug.cgi?id=635 |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | better reporting on gpr comparisons |
commit | commitdiff | tree |
2021-04-30 |
Luke Kenneth... | set up LoadStore1 in ConfigMemoryPortInterface and... |
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next |