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soc.git
2021-04-25
Luke Kenneth...
add TODO comment in dcache
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2021-04-25
Luke Kenneth...
move Signals in dcache to relevant context
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2021-04-25
Luke Kenneth...
dcache Elif used where If should have been
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2021-04-25
Luke Kenneth...
whoops should be cyc & ~ack
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2021-04-25
Luke Kenneth...
hard-code dcache stall signal to non-pipelined mode
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2021-04-24
Luke Kenneth...
increase memory size in dcache test
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2021-04-24
Luke Kenneth...
increase size of random dcache testing by 10
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2021-04-24
Luke Kenneth...
fix errors in dcache unit test
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2021-04-24
Luke Kenneth...
whitespace
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2021-04-24
Luke Kenneth...
add additional external libre-soc sphinx references...
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2021-04-24
Luke Kenneth...
add additional external libre-soc sphinx references
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2021-04-24
Luke Kenneth...
remove code moved to openpower-isa repo
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2021-04-23
Luke Kenneth...
add comments on TestIssuer TestRunner
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2021-04-23
Luke Kenneth...
comment tests back in
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2021-04-23
Luke Kenneth...
fix import error
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2021-04-23
Luke Kenneth...
error in setting fast regs test values
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2021-04-23
Luke Kenneth...
import from openpower.tests
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2021-04-23
Luke Kenneth...
whitespace
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2021-04-23
Luke Kenneth...
move logical tests to openpower.test
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2021-04-23
Luke Kenneth...
add trap test cases
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2021-04-23
Luke Kenneth...
move SPR tests to openpower.test
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2021-04-23
Luke Kenneth...
move branch test cases to openpower.test
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2021-04-23
Luke Kenneth...
move LDST tests to openpower.test
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2021-04-23
Luke Kenneth...
move mul tests to openpower.test
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2021-04-23
Luke Kenneth...
move div tests to openpower.test
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2021-04-23
Luke Kenneth...
move div tests to openpower.test
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2021-04-23
Luke Kenneth...
move ALU test cases to openpower.test
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2021-04-23
Luke Kenneth...
move MMU Testcase to openpower.test
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2021-04-23
Luke Kenneth...
move CR test cases to openpower.test
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2021-04-23
Luke Kenneth...
move shiftrot test cases to openpower.test
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2021-04-23
Luke Kenneth...
import from openpower.endian
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2021-04-23
Luke Kenneth...
use openpower.test.common
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2021-04-23
Luke Kenneth...
remove openpower-isa submodule
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2021-04-23
Luke Kenneth...
submodule update, can probably delete it though, now
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2021-04-23
Luke Kenneth...
move more files to openpower-isa
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2021-04-23
Luke Kenneth...
move to import from openpower-isa for reg enums
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2021-04-23
Luke Kenneth...
svanalysis and pywriter now command-line scripts
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2021-04-23
Luke Kenneth...
removed submodule
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2021-04-23
Luke Kenneth...
remove pseudo, moved to openpower-isa
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2021-04-23
Luke Kenneth...
remove simulator directory, moved to openpower-isa
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2021-04-23
Luke Kenneth...
more openpower-isa conversion
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2021-04-23
Luke Kenneth...
correct migration of openpower-isa
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2021-04-23
Luke Kenneth...
more openpower import conversion
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2021-04-23
Luke Kenneth...
more openpower import conversion
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2021-04-23
Luke Kenneth...
move over to from openpower imports
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2021-04-23
Luke Kenneth...
move over to openpower-isa repo
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2021-04-23
Luke Kenneth...
move over to openpower-isa
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2021-04-23
Luke Kenneth...
moving more over to openpower-isa repo
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2021-04-23
Luke Kenneth...
removing more as moved over to openpower-isa
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2021-04-23
Luke Kenneth...
submodule update
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2021-04-22
Luke Kenneth...
add debugging and buffering to CacheRam
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2021-04-22
Luke Kenneth...
whitespace
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2021-04-22
Luke Kenneth...
r1.end_row_ix off-by-one in dcache
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2021-04-22
Luke Kenneth...
sync missing in dcache
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2021-04-22
Luke Kenneth...
dcache.py code-comments
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2021-04-22
Luke Kenneth...
cleanup dcache
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2021-04-22
Luke Kenneth...
error using sync, should have been comb
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2021-04-22
Cesar Strauss
Implement CR predication
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2021-04-21
Cesar Strauss
CR sub-fields are stored in MSB0 order
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2021-04-21
Luke Kenneth...
experimenting with dcache
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2021-04-21
Tobias Platen
testcase: pass PRTBL to mmu
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2021-04-21
Cesar Strauss
Add CR predication test case for TestIssuer
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2021-04-21
Cesar Strauss
Fix comment in CR predication test case
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2021-04-21
Cesar Strauss
Fix sense of "invert" signal
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2021-04-20
Luke Kenneth...
add enable MMU option to issuer_verilog.py
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2021-04-20
Luke Kenneth...
cannot pass in arguments to Core - must be done with...
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2021-04-20
Luke Kenneth...
use soc.bus.sram instead of nmigen_soc.wishbone.sram
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2021-04-20
Luke Kenneth...
add wishbone sram.py (move from nmigen-soc)
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2021-04-19
Luke Kenneth...
give independent names to spblock512w64b8ws
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2021-04-18
Luke Kenneth...
give spblock512 a name as a submodule
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2021-04-18
Luke Kenneth...
create signal on test_issuer which gives PLL clk_sel_i...
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2021-04-18
Luke Kenneth...
rename SPBlock_512W64B8W to lowercase
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2021-04-18
Luke Kenneth...
submodule update
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2021-04-18
Luke Kenneth...
rename PLL pins to match LIP6.fr PLL
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2021-04-18
Luke Kenneth...
core_stopped_i unused: remove
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2021-04-18
Luke Kenneth...
submodule update
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2021-04-18
Luke Kenneth...
submodule update
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2021-04-18
Luke Kenneth...
add pypi upload to Makefile
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2021-04-18
Luke Kenneth...
add OS Independent classifier
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2021-04-18
Luke Kenneth...
update README
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2021-04-18
Luke Kenneth...
update setup.py to make it "safe" for uploading to...
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2021-04-17
Luke Kenneth...
experiment with alternative PID in radix mmu
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2021-04-17
Luke Kenneth...
pass in SPRs each time on radix test
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2021-04-17
Luke Kenneth...
add LD/ST radix unit test
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2021-04-17
Cesar Strauss
Implement 1<<r3 directly by a shift
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2021-04-17
Tobias Platen
radixmmu: fix my mistake about pgbase size
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2021-04-16
Luke Kenneth...
submodule update
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2021-04-16
Luke Kenneth...
jtag utils, send tms before tck
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2021-04-16
Tobias Platen
pass the "old" value of shift to _new_lookup
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2021-04-16
Luke Kenneth...
sigh, new_shift wrong bitwidth
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2021-04-16
Luke Kenneth...
put mbits back into segment_check (like it is in microwatt)
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2021-04-16
Luke Kenneth...
radixmmu cleanup
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2021-04-16
Luke Kenneth...
call addrshift and get_pgtable_addr inside while loop...
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2021-04-16
Luke Kenneth...
code-cleanup in radixmmu
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2021-04-15
Luke Kenneth...
whitespace and corrections to NLS, RTS1, RTS2
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2021-04-15
Tobias Platen
fix radix testcase
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2021-04-15
Luke Kenneth...
concat en_sigs together in JTAG to make sure they are...
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2021-04-15
Luke Kenneth...
add icachemmu option to ISACaller
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2021-04-14
Luke Kenneth...
submodule update
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2021-04-14
Luke Kenneth...
whitespace
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