soc.git
2020-05-13 Michael NolanModify alu test to put reg1 *OR* reg3 into alu input A
2020-05-13 Michael NolanUpdate TODO
2020-05-13 Luke Kenneth... remove operand c from ALU in/out
2020-05-12 Luke Kenneth... temporary reorg of reg/immediate reading
2020-05-12 Luke Kenneth... add 3rd register input to ALUInputData
2020-05-12 Luke Kenneth... connect LDSTMulti to 6600 Scoreboard
2020-05-12 Luke Kenneth... when doing LD-immediate only acknowledge register 1...
2020-05-12 Michael NolanAdd new shift_rot FU for shifts and rotates
2020-05-12 Michael NolanRemove rotates and shifts from alu
2020-05-11 Michael NolanMassively spead up test_pipe_caller.py
2020-05-11 Michael NolanRevert "Greatly speed up test_pipe_caller.py"
2020-05-11 Michael NolanGreatly speed up test_pipe_caller.py
2020-05-11 Luke Kenneth... comments from discussion
2020-05-11 Michael NolanReverse bit order for cr0 in proof
2020-05-11 Michael NolanCheck output of cr0 from alu
2020-05-11 Michael NolanAdd carry in input to alu testbench
2020-05-11 Michael NolanAdd ability to specify initial state for SPRs
2020-05-11 Michael NolanFix proof_input_stage.py
2020-05-11 Michael NolanFix rlwimi by reordering the inputs *again*
2020-05-11 Michael NolanRe-enable rlwinm test
2020-05-11 Michael NolanCheck write register number too
2020-05-11 Michael NolanReorder the register reads so the field in read_reg2...
2020-05-11 Michael NolanHave test_pipe_caller actually read from the registers...
2020-05-11 Michael NolanActually implement rlwimi
2020-05-11 Luke Kenneth... comment input signals
2020-05-11 Luke Kenneth... cleanup rotator.py
2020-05-11 Luke Kenneth... add docstring, missing return module
2020-05-11 Luke Kenneth... start cleanup of rotator.py, Cat order is inverted
2020-05-11 Luke Kenneth... convert microwatt rotator to nmigen (first draft)
2020-05-10 Michael NolanAdd test for rlwnm
2020-05-10 Michael NolanImplement rlwimi as well
2020-05-10 Michael NolanImplement rlwinm in alu
2020-05-10 Michael NolanAdd test for rlwinm
2020-05-10 Michael NolanReduce BMC depth on proof_main_stage.py
2020-05-10 Luke Kenneth... use temporary python vars rather than copy signals...
2020-05-09 Michael NolanAdd shift left and shift right to main stage proof
2020-05-09 Luke Kenneth... sigh ton of syntax errors
2020-05-09 Luke Kenneth... bit of reorg, trick on add - put carry in into the LSB
2020-05-09 Luke Kenneth... comment output stage
2020-05-09 Luke Kenneth... comment maskgen
2020-05-09 Michael NolanHandle algebraic shifts too
2020-05-09 Michael NolanImplement logical shift right
2020-05-09 Michael NolanAdd support for sld
2020-05-09 Michael NolanChange shift left to be implemented with rotate and...
2020-05-09 Michael NolanAdd mask generator for shift class instructions
2020-05-09 Michael NolanAdd shift left opcode to main_stage
2020-05-09 Michael NolanFix broken mask when x == y
2020-05-09 Michael NolanAdd right shift test to test_caller.py
2020-05-09 Michael NolanAdd shift test to test_caller, fix fixedshift being...
2020-05-09 Michael NolanFix helpers.py not playing nicely with selectableInts
2020-05-09 Michael NolanAdd reversed add and subtract, as well as lshift and...
2020-05-09 Luke Kenneth... comment where ALUIntermediateData to go
2020-05-09 Luke Kenneth... TODO on AluIntermediateData
2020-05-09 Luke Kenneth... missing sticky-overflow pass-through from middle stage
2020-05-09 Luke Kenneth... pass through sticky-overflow
2020-05-09 Luke Kenneth... remove unneeded class
2020-05-09 Luke Kenneth... clarifying comments
2020-05-09 Michael NolanMinor cleanup
2020-05-09 Luke Kenneth... preliminary test for LD/ST "update" mode working
2020-05-09 Luke Kenneth... document PowerOp
2020-05-08 Luke Kenneth... add comments
2020-05-08 Luke Kenneth... add ALUFirstInputData
2020-05-08 Luke Kenneth... send address to memory only for one cycle and acknowled...
2020-05-08 Luke Kenneth... experimenting
2020-05-08 Luke Kenneth... working indexed version of LD/ST CompUnit
2020-05-08 Luke Kenneth... hmmm i think LD/ST Comp Unit might actually be working...
2020-05-08 Michael NolanOops, forgot pipeline.py
2020-05-08 Michael NolanAdd tests for immediates, add subf to tests
2020-05-08 Michael NolanAdd comments about the purpose of each alu stage
2020-05-08 Michael NolanAdd test for alu against simulator
2020-05-08 Michael NolanAdd assertions for output stage cr0
2020-05-08 Michael NolanAdd output stage
2020-05-08 Michael NolanAdd and or and xor to main_stage
2020-05-08 Michael NolanAdd carry in and out
2020-05-08 Michael NolanHave input_stage set the b operand to imm_data if it...
2020-05-08 Michael NolanAdd extra bits (carry, overflow, etc) to input and...
2020-05-08 Michael NolanBegin adding main ALU stage
2020-05-08 Michael NolanConvert alu to use the op in ctx
2020-05-08 Michael NolanAdd FPPipeContext to alu pipe_data
2020-05-08 Luke Kenneth... almost got LD/ST CompUnit working
2020-05-08 Luke Kenneth... prototype LD/ST L0 cache/buffer was bouncing address...
2020-05-08 Michael NolanAdd handling of A inversion and B input
2020-05-08 Michael NolanBegin adding input stage of alu
2020-05-08 Michael NolanAdd pipe data for ALU pipeline
2020-05-08 Michael NolanUpdate gitignore in isa dir
2020-05-08 Michael NolanSeparate out ALU Input record from alu_hier.py
2020-05-07 Michael NolanAdd test_branch_loop_ctr
2020-05-07 Michael NolanAdd tests for conditional branches
2020-05-07 Luke Kenneth... move unused simulator code out the way
2020-05-07 Luke Kenneth... testing LD without ST
2020-05-07 Michael NolanOoops, forgot comparefixed.patch
2020-05-07 Michael NolanGet test_cmp working
2020-05-07 Michael NolanFix test_mtcrf. Test has been verified against qemu
2020-05-07 Michael NolanMake FieldSelectableInt accept slices for set and get
2020-05-07 Michael NolanAdd handling of add with comparison
2020-05-07 Michael NolanFix bug with comparisons in selectable_int.py
2020-05-07 Michael NolanAdd test_mfcr
2020-05-07 Luke Kenneth... continuing debugging of LD/ST CompUnit FSM and unit...
2020-05-07 Luke Kenneth... partially-debugged ld/st comp unit using new PortInterface
2020-05-06 Michael NolanRe-enable test_mtcrf
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