2021-02-17 |
Cesar Strauss | Add traces to debug SVP64 prefix decoding issues |
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2021-02-17 |
Cesar Strauss | Setup SVSTATE, from the test settings, at the start |
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2021-02-16 |
Cesar Strauss | Fix MSB0 issues for SVP64 |
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2021-02-16 |
Tobias Platen | mmureq handling |
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2021-02-16 |
Tobias Platen | dcache error handling |
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2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-16 |
Luke Kenneth... | ordering wrong on svstate in ISACaller |
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2021-02-16 |
Luke Kenneth... | adapt botchify so it can be used for 31- or 15- etc... |
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2021-02-16 |
Luke Kenneth... | add indicator to PowerDecoder2 when no outputs are... |
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2021-02-15 |
Cole Poirier | remove file experiment/formal/proof_icache.py as it... |
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2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
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2021-02-15 |
Cesar Strauss | Simplify obtaining the PC from the register file |
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2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-14 |
Cesar Strauss | Show traces for the register numbers of the current... |
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2021-02-14 |
Cesar Strauss | Fix width of the "extra" input on the Extra decoder |
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2021-02-14 |
Cesar Strauss | Fix conversion to MSB0 |
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2021-02-14 |
Cesar Strauss | Remove obsolete comment |
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2021-02-14 |
Luke Kenneth... | add comments to TestIssuer |
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2021-02-14 |
Luke Kenneth... | add srcstep onto Vectorised GPRs in PowerDecoder2 |
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2021-02-14 |
Luke Kenneth... | add TestRunner comments |
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2021-02-14 |
Luke Kenneth... | add Regfiles comments |
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2021-02-14 |
Luke Kenneth... | add SVSTATE reading to TestIssuer |
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2021-02-14 |
Luke Kenneth... | add SVSTATE to CoreState |
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2021-02-14 |
Luke Kenneth... | add extra FSM explanatory comments to TestIssuer |
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2021-02-13 |
Luke Kenneth... | use function for getting instruction from 32/64 bit... |
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2021-02-13 |
Cesar Strauss | Fetch and decode the SVP64 prefix |
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2021-02-13 |
Tobias Platen | OP_TLBIE must in be instr_is_priv |
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2021-02-13 |
Tobias Platen | keep commits to under 80 chars |
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2021-02-13 |
Cesar Strauss | Check the PC value at the end of each instruction |
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2021-02-13 |
Cesar Strauss | Skip vector test case, and add a scalar case |
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2021-02-13 |
Cesar Strauss | Fix imports and whitespace |
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2021-02-13 |
Luke Kenneth... | update svp64 unit test comments |
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2021-02-13 |
Tobias Platen | forward microwatt mmu specific SPR: PID and PRTBL |
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2021-02-13 |
Luke Kenneth... | add SVP64 TestIssuer separate unit test |
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2021-02-13 |
Luke Kenneth... | split out TestRunner into separate module |
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2021-02-13 |
Cesar Strauss | Fix SVP64 translator to yield the unaltered instruction |
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2021-02-12 |
Luke Kenneth... | add one SVP64 ALU test case to get started |
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2021-02-12 |
Luke Kenneth... | add SVSTATE to TestCase infrastructure for use in TestI... |
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2021-02-12 |
Luke Kenneth... | add skip of instruction if SVSTATE.VL=0 in ISACaller |
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2021-02-12 |
Luke Kenneth... | validate all registers to make sure no damage occurs... |
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2021-02-12 |
Luke Kenneth... | add srcstep and correct PC-advancing during Sub-PC... |
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2021-02-12 |
Luke Kenneth... | comments |
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2021-02-12 |
Luke Kenneth... | add in SVSTATE.srcstep update, loop from 0 to VL-1 |
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2021-02-12 |
Luke Kenneth... | allow PC to update by 8 in SVP64 mode |
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2021-02-12 |
Luke Kenneth... | fix setting of SVSTATE.VL and MVL |
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2021-02-12 |
Luke Kenneth... | add in SVSTATE to ISACaller, not used, just passed in |
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2021-02-11 |
Luke Kenneth... | comments in TestIssuer for SVP64PrefixDecoder |
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2021-02-10 |
Luke Kenneth... | add svp64 reg decode detection to ISACaller output |
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2021-02-10 |
Luke Kenneth... | starting to add SVP64 register EXTRA-read and isvec... |
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2021-02-10 |
Luke Kenneth... | comment update |
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2021-02-09 |
colepoirier | add missing newline at end of experiment/formal/.gitignore |
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2021-02-09 |
colepoirier | fix erroneous removal of proof* from experiment/formal... |
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2021-02-07 |
colepoirier | add skeleton implementation of experiment/formal/proof_... |
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2021-02-07 |
colepoirier | icache.py fix formatting |
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2021-02-07 |
colepoirier | Modify experiment/formal/.gitignore because was prevent... |
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2021-02-06 |
Cesar Strauss | Fix whitespace |
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2021-02-06 |
Cesar Strauss | Extract the fetch FSM out from the main FSM |
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2021-02-05 |
Tobias Platen | fix hanging simulation |
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2021-02-04 |
Tobias Platen | src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave |
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2021-02-04 |
Tobias Platen | update test_issuer_mmu_data_path.py to handle SPRs |
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2021-02-04 |
Tobias Platen | pass SPR MicroOp to MMU function unit |
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2021-02-03 |
Luke Kenneth... | nope - need it to be zero if not identified as svp64 |
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2021-02-03 |
Luke Kenneth... | actually no need to mux in the svp64_rm, just the id... |
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2021-02-03 |
Luke Kenneth... | add SVP64PowerDecoder, extracts svp64 remap if correctl... |
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2021-02-01 |
Luke Kenneth... | ISACaller, in svp64 mode, read the next 32 bits when... |
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2021-02-01 |
Tobias Platen | extending the GTKWave document in test_issuer when... |
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2021-02-01 |
Luke Kenneth... | sort out SelectableInt bit-ordering for identifying... |
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2021-02-01 |
Luke Kenneth... | construct the assembly-code prefix and base v3.0B in... |
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2021-02-01 |
Cesar Strauss | Add GTKWave document to test_issuer |
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2021-01-31 |
Cesar Strauss | Fix loop test and enable it |
commit | commitdiff | tree |
2021-01-31 |
Luke Kenneth... | start an ISACaller SVP64 unit test |
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2021-01-31 |
Luke Kenneth... | test SVP64 major opcode, start checking if it is EXT001... |
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2021-01-31 |
Luke Kenneth... | adjusting ISACaller unit test to use ISACaller.setup_one() |
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2021-01-31 |
Luke Kenneth... | fix ISACaller unit test |
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2021-01-31 |
Tobias Platen | fix two syntax errors in src/soc/decoder/isa/caller.py |
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2021-01-31 |
Luke Kenneth... | SVP64 Remap Fields structures for ISACaller |
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2021-01-31 |
Luke Kenneth... | remove sv_rm from PowerDecoder register decoders |
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2021-01-31 |
Luke Kenneth... | add SVSTATE SPR sub-field accessor class to ISACaller |
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2021-01-31 |
Luke Kenneth... | move SVP64 Extra reg decoding into main PowerDecoder... |
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2021-01-31 |
Luke Kenneth... | update submodule |
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2021-01-30 |
Luke Kenneth... | move CR in/out SVP64 EXTRA decoders into PowerDecoder |
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2021-01-30 |
Luke Kenneth... | add SVP64 CR out extending to 7-bit in PowerDecoder2 |
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2021-01-30 |
Luke Kenneth... | add SVP64 CR EXTRA field-extension, from 3-bit to 7... |
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2021-01-30 |
Luke Kenneth... | extend CR registers in Decode2ToExecute1Type to 7 bit |
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2021-01-30 |
Luke Kenneth... | add SVP64CRExtra class to PowerDecoder2, turns 3-bit... |
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2021-01-30 |
Luke Kenneth... | split out SVEXTRA field selection/decoding into separat... |
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2021-01-30 |
Luke Kenneth... | whoops update PowerDecoder2 svp64 comments, reg sizes... |
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2021-01-30 |
Luke Kenneth... | add SVP64 EXTRA decoding to RB, RC and RT (out) in... |
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2021-01-30 |
Luke Kenneth... | add first SVP64 7-bit register context decoder to Power... |
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2021-01-29 |
Luke Kenneth... | add SVP64RM record to PowerDecoder2 |
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2021-01-29 |
Luke Kenneth... | increase register number sizes from 5 to 7 |
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2021-01-29 |
Luke Kenneth... | syntax corrections, also size of maxvl was wrong |
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2021-01-29 |
Luke Kenneth... | add SVP64 RM (Remap) Record |
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2021-01-29 |
Luke Kenneth... | adjust SVP64RM class to output more PowerDecoder-friend... |
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2021-01-29 |
Luke Kenneth... | adjust how register copy/setup is done in PowerDecoder2 |
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2021-01-29 |
Luke Kenneth... | add SV etype/ptype to power decoder |
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2021-01-29 |
Luke Kenneth... | whoops syntax error. submodule update |
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2021-01-29 |
Luke Kenneth... | start adding svp64 enums |
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2021-01-29 |
Luke Kenneth... | use new svp64-augmented csv reader in PowerDecoder |
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2021-01-29 |
Luke Kenneth... | whoops missed out "+" on explicit license listing |
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next |