| 2020-09-24 | 
Luke Kenneth...  | enable GPIO pads through C4M JTAG | 
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| 2020-09-24 | 
Luke Kenneth...  | c4m iopad integration working | 
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| 2020-09-24 | 
Cole Poirier | icache.py add some missing lines from icache.vhdl,...  | 
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| 2020-09-24 | 
Cole Poirier | mem_types.py wb_types.py add name constructor to all...  | 
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| 2020-09-24 | 
Cole Poirier | icache.py fixed all errors that raised python exception...  | 
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| 2020-09-24 | 
Cesar Strauss | Fix whitespace, remove unused imports | 
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| 2020-09-24 | 
Luke Kenneth...  | brackets round imports looks cleaner? | 
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| 2020-09-24 | 
Luke Kenneth...  | add jtag c4m pins which gives us a way to connect IO...  | 
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| 2020-09-24 | 
Cesar Strauss | Use nmutil simulator module to simplify choosing among...  | 
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| 2020-09-23 | 
Luke Kenneth...  | cs_n and cke in sdram need to match in length | 
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| 2020-09-23 | 
Luke Kenneth...  | change litex sdram pinouts to ASIC type | 
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| 2020-09-23 | 
Luke Kenneth...  | redo litex SDCard to send out data/cmd o/i/en pins | 
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| 2020-09-23 | 
Luke Kenneth...  | sort out GPIO with i/o/oe in ls180 | 
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| 2020-09-23 | 
Luke Kenneth...  | add ls180 pinmap text file | 
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| 2020-09-23 | 
Luke Kenneth...  | attempt GPIO bi-directional | 
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| 2020-09-23 | 
Luke Kenneth...  | add I2C master to ls180 | 
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| 2020-09-22 | 
Luke Kenneth...  | add 2 PWMs (quick, easy to do) | 
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| 2020-09-22 | 
Luke Kenneth...  | move dmi_sim to separate module | 
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| 2020-09-22 | 
Jacob Lifshay | update submodule url | 
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| 2020-09-22 | 
Jacob Lifshay | Revert "disable pia in div tests" | 
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| 2020-09-22 | 
Luke Kenneth...  | add openocd.cfg experiment | 
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| 2020-09-22 | 
Luke Kenneth...  | create a JTAG platform and connect it up.  jtagremote...  | 
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| 2020-09-22 | 
Luke Kenneth...  | add jtagremote to litex sim, add new "variant" to core...  | 
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| 2020-09-22 | 
Luke Kenneth...  | link litex ls180soc JTAG pads | 
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| 2020-09-22 | 
Luke Kenneth...  | add jtag wishbone and jtag ports to libresoc litex...  | 
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| 2020-09-22 | 
Luke Kenneth...  | add jtag interface to issuer_verilog | 
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| 2020-09-22 | 
Luke Kenneth...  | add sys_rst to Clock Reset Generator | 
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| 2020-09-22 | 
Luke Kenneth...  | add JTAG IOpads and rename rst to sys_rst | 
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| 2020-09-22 | 
Luke Kenneth...  | add similar platforms to ls180.py | 
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| 2020-09-22 | 
Luke Kenneth...  | add JTAG bus module | 
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| 2020-09-22 | 
Luke Kenneth...  | split out dmi2jtag into own unit test | 
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| 2020-09-22 | 
Luke Kenneth...  | submodule update | 
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| 2020-09-22 | 
Cesar Strauss | Port soc.experiment.alu_fsm to the new way of invoking...  | 
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| 2020-09-22 | 
Luke Kenneth...  | disable pia in div tests | 
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| 2020-09-22 | 
Luke Kenneth...  | add MMU (commented out) | 
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| 2020-09-21 | 
Luke Kenneth...  | add missing file | 
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| 2020-09-21 | 
Luke Kenneth...  | add quick wishbone jtag test | 
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| 2020-09-21 | 
Luke Kenneth...  | experiment set dmi msr read | 
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| 2020-09-21 | 
Luke Kenneth...  | add DMI JTAG test | 
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| 2020-09-21 | 
Luke Kenneth...  | add JTAG basic unit test | 
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| 2020-09-21 | 
Luke Kenneth...  | arg complete rewrite of JTAG2DMI, based it on staf...  | 
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| 2020-09-20 | 
Cesar Strauss | Add induction proof for the FSM Shifter | 
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| 2020-09-20 | 
Cesar Strauss | Add bounded proof to FSM Shifter | 
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| 2020-09-20 | 
Cesar Strauss | Let the formal engine create some test cases for the...  | 
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| 2020-09-20 | 
Luke Kenneth...  | resolve issues in async sim: must not drive async clock...  | 
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| 2020-09-20 | 
Luke Kenneth...  | still experimenting with async FF sync | 
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| 2020-09-20 | 
Luke Kenneth...  | continuing async clock experimenting | 
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| 2020-09-20 | 
Luke Kenneth...  | add an async clock synchronizer experiment | 
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| 2020-09-20 | 
Luke Kenneth...  | first version code-morph on dmi2jtag | 
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| 2020-09-19 | 
Luke Kenneth...  | add pc_o not connected | 
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| 2020-09-19 | 
Luke Kenneth...  | set ROM to empty, set SRAM to tiny 0x200, get things...  | 
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| 2020-09-19 | 
Cesar Strauss | Remove demonstration code | 
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| 2020-09-19 | 
Luke Kenneth...  | urk. wishbone slave devices declared incorrectly (I...   semi_working_ecp5 | 
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| 2020-09-19 | 
Luke Kenneth...  | disable internal RAM set SRAM to much smaller | 
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| 2020-09-19 | 
Luke Kenneth...  | shrink size of SRAM to 8k, move things around | 
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| 2020-09-19 | 
Luke Kenneth...  | add (disabled) tri-state GPIO | 
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| 2020-09-19 | 
Luke Kenneth...  | remove the gpio peripheral which was previously hard...  | 
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| 2020-09-19 | 
Luke Kenneth...  | add 3x EINTs to ls180soc | 
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| 2020-09-18 | 
Luke Kenneth...  | add SPI, sdcard, preliminary GPIO to ls180 pinouts | 
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| 2020-09-18 | 
Luke Kenneth...  | argh got fed up trying to shoe-horn into sim.py | 
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| 2020-09-18 | 
Luke Kenneth...  | can remove unneeded overrides of Prev/Next Control | 
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| 2020-09-17 | 
Jacob Lifshay | add divwe regression test case | 
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| 2020-09-17 | 
Jacob Lifshay | re-enable test case -- no longer goes into an infinite...  | 
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| 2020-09-17 | 
Jacob Lifshay | fix bug #492 | 
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| 2020-09-17 | 
Jacob Lifshay | replace sim._state.timeline.now with sim._engine.now | 
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| 2020-09-17 | 
Luke Kenneth...  | add versa ecp5 fpga litex build script | 
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| 2020-09-16 | 
Cole Poirier | complete first translation pass of dmi_dtm_xilinx.vhdl...  | 
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| 2020-09-16 | 
Luke Kenneth...  | make a start on LS180 platform | 
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| 2020-09-16 | 
Cole Poirier | initial commit of JTAGToDMI debug interface translated...  | 
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| 2020-09-16 | 
Cole Poirier | add template file/starting point (copy of litex/boards...  | 
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| 2020-09-15 | 
Luke Kenneth...  | add back (totally confusing) accidentally-removed code...  | 
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| 2020-09-15 | 
Luke Kenneth...  | instantiate MMU from AllFunctionUnits | 
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| 2020-09-15 | 
Luke Kenneth...  | do not need FAST regs in MMU | 
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| 2020-09-15 | 
Luke Kenneth...  | comment mmu test | 
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| 2020-09-15 | 
Luke Kenneth...  | add edge-triggering to dcache/mmu "valid" | 
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| 2020-09-15 | 
Luke Kenneth...  | add set MTSPR prtbl to mmu unit test | 
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| 2020-09-15 | 
Luke Kenneth...  | add OP_MFSPR to mmu | 
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| 2020-09-15 | 
Luke Kenneth...  | use convenience vars | 
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| 2020-09-15 | 
Luke Kenneth...  | add OP_TLBIE to mmu fsm | 
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| 2020-09-15 | 
Luke Kenneth...  | add OP_DCBZ to mmu fsm, needs RA to be added to MMU...  | 
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| 2020-09-15 | 
Luke Kenneth...  | add MMU MTSPR connection into FSM | 
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| 2020-09-15 | 
Luke Kenneth...  | add in MMU and DCache into MMU FSM | 
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| 2020-09-15 | 
Luke Kenneth...  | moved PLRU to nmutil | 
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| 2020-09-15 | 
Luke Kenneth...  | add mmu fsm | 
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| 2020-09-15 | 
Luke Kenneth...  | remove more (confusing/spurious) types, should be in...  | 
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| 2020-09-15 | 
Luke Kenneth...  | remove more (confusing/spurious) types, should be in...  | 
commit | commitdiff | tree | 
| 2020-09-15 | 
Luke Kenneth...  | remove more (confusing/spurious) types, should be in...  | 
commit | commitdiff | tree | 
| 2020-09-15 | 
Luke Kenneth...  | removed (confusing/spurious) types, should be in .pyi...  | 
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| 2020-09-15 | 
Luke Kenneth...  | add MMU FunctionUnit | 
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| 2020-09-15 | 
Luke Kenneth...  | mmu uses RB, go with it | 
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| 2020-09-15 | 
Luke Kenneth...  | add OP_TLBIE | 
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| 2020-09-15 | 
Luke Kenneth...  | add mmu initial pipe_data.py | 
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| 2020-09-15 | 
Luke Kenneth...  | add extra "modes" to PortInterface | 
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| 2020-09-15 | 
Luke Kenneth...  | syntax error correction | 
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| 2020-09-15 | 
Luke Kenneth...  | add inline comments into icache.py | 
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| 2020-09-14 | 
Cole Poirier | icache.py add missing funciton bodies, add missing...  | 
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| 2020-09-14 | 
Luke Kenneth...  | increase TLB_NUM_WAYS to 4 | 
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| 2020-09-14 | 
Luke Kenneth...  | vhdl conversion not really working for plru | 
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| 2020-09-14 | 
Luke Kenneth...  | add array signal names | 
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| 2020-09-14 | 
Luke Kenneth...  | rename plru input | 
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| next |