2021-02-28 |
Luke Kenneth... | start on SVP64 RM Mode decoder |
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2021-02-28 |
Luke Kenneth... | more SVP64 enums |
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2021-02-28 |
Luke Kenneth... | add SVP64 RM sub-field enums |
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2021-02-28 |
Luke Kenneth... | move SVP64 Extra decoders to separate module |
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2021-02-28 |
Luke Kenneth... | fix syntax error |
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2021-02-28 |
Luke Kenneth... | move SVP64PrefixDecoder to separate module |
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2021-02-28 |
Luke Kenneth... | add PowerDecoder.no_in_vec |
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2021-02-28 |
Luke Kenneth... | add svp64_instrs to power_svp64 |
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2021-02-28 |
Tobias Platen | fix Bug 607 - unnecessary code added related to MMU... |
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2021-02-28 |
Tobias Platen | fix Bug 603 - use SPR names/numbers from sprs.csv |
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2021-02-27 |
Luke Kenneth... | use PowerDecoder2.no_out_vec instead of manual vector... |
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2021-02-27 |
Luke Kenneth... | add corresponding VL=0 unit test as from 161b7d67b... |
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2021-02-27 |
Cesar Strauss | Add traces for the new FSM |
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2021-02-26 |
Cesar Strauss | Add a vector case with VL == 0 |
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2021-02-26 |
Luke Kenneth... | comment on CoreState |
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2021-02-26 |
Luke Kenneth... | remove sv_changed input to fetch_fsm, add it to issue_f... |
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2021-02-26 |
Luke Kenneth... | moving new_svstate and update_svstate into issue FSM... |
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2021-02-26 |
Luke Kenneth... | move fetch_insn_o into issue_fsm TestIssuer |
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2021-02-26 |
Luke Kenneth... | add comments, missing that VL loop ends after execution... |
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2021-02-26 |
Cesar Strauss | Implement a decode/issue FSM between fetch and execute |
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2021-02-24 |
Tobias Platen | wb_get: write outputs to seperate logfile too |
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2021-02-24 |
Tobias Platen | update mmu testcase |
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2021-02-24 |
Tobias Platen | test_runner.py: add needed imports |
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2021-02-24 |
Luke Kenneth... | add comments explaining split |
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2021-02-24 |
Luke Kenneth... | move DecodeCROut/In (at last) out of PowerDecoderSubset... |
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2021-02-24 |
Luke Kenneth... | start making write_cr0 independent of DecodeCROut |
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2021-02-23 |
Tobias Platen | deduplicate |
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2021-02-23 |
Luke Kenneth... | add note that SVSTATE has changed, this will allow... |
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2021-02-22 |
Cesar Strauss | Fix typo when calculating PowerDecoder2.no_out_vec |
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2021-02-22 |
Luke Kenneth... | move setting of NIA into fetch FSM in TestIssuer |
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2021-02-22 |
Luke Kenneth... | whoops |
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2021-02-22 |
Luke Kenneth... | moving PC-setting (NIA) out of execute_fsm in TestIssuer |
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2021-02-22 |
Luke Kenneth... | rename inter-FSM handshake signals in TestIssuer |
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2021-02-21 |
Luke Kenneth... | err trying to put in some FSM handshake signals, gettin... |
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2021-02-21 |
Luke Kenneth... | comment for where SVSTATE FSM should go |
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2021-02-21 |
Luke Kenneth... | add CR out vector detection to PowerDecoder2 no_out_vec |
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2021-02-21 |
Cesar Strauss | The field selection function was moved to nmutil.util |
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2021-02-21 |
Cesar Strauss | Hide the register augmentation traces by default |
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2021-02-21 |
Luke Kenneth... | move execute_fsm to separate function in TestIssuer |
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2021-02-21 |
Luke Kenneth... | move fetch_fsm to separate function in TestIssuer |
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2021-02-21 |
Luke Kenneth... | add JTAG enable/disable of 4k SRAMs |
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2021-02-21 |
Cesar Strauss | The new version of "sel" is smart enough to find a... |
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2021-02-21 |
Luke Kenneth... | add comments for Mode field in SVP64Asm |
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2021-02-21 |
Luke Kenneth... | comments in SVP64RMFields |
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2021-02-21 |
Cesar Strauss | Use the new selection field function from nmutil |
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2021-02-21 |
Cesar Strauss | Use symbolic values as field sizes |
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2021-02-21 |
Cesar Strauss | Replace all hardcoded shifts into RM by usage of SVP64R... |
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2021-02-21 |
Luke Kenneth... | create SVP64CROffs consts for when SVP64 Vector-of... |
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2021-02-20 |
Luke Kenneth... | comments on sv.add. Rc=1 unit test |
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2021-02-20 |
Luke Kenneth... | add in Vectorised CRs when Rc=1 into ISACaller |
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2021-02-20 |
Luke Kenneth... | add CR1 to DecodeCRIn/Out |
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2021-02-20 |
Luke Kenneth... | add some debug checking to get_pdecode_cr_out |
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2021-02-20 |
Luke Kenneth... | add crossreference to bug #603 |
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2021-02-20 |
Luke Kenneth... | add more debug output to get_pdecode_cr_out |
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2021-02-20 |
Cesar Strauss | Actually forward the field width to field_slice() |
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2021-02-20 |
Cesar Strauss | Assemble the SV64 prefix from its subfields using SVP64... |
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2021-02-20 |
Luke Kenneth... | start on CRs in SVP64 mode |
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2021-02-20 |
Luke Kenneth... | fix SVP64Asm Rc=1 assembly |
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2021-02-20 |
Luke Kenneth... | add black-box attribute to 4k SRAM cell |
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2021-02-20 |
Cesar Strauss | Fix more MSB0 issues in comments |
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2021-02-20 |
Cesar Strauss | Replace more hardcoded constants with symbolic field... |
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2021-02-20 |
Luke Kenneth... | increment CRs based on srcstep, see what happens |
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2021-02-20 |
Luke Kenneth... | add litex wishbone interconnect to 4x 4k SRAMs |
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2021-02-20 |
Luke Kenneth... | add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... |
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2021-02-20 |
Luke Kenneth... | add option for QTY 4x 4k SRAM blocks (not added yet... |
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2021-02-20 |
Luke Kenneth... | add Wishbone-wrapped SPBlock_512W64B8W |
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2021-02-20 |
Luke Kenneth... | whoops set ROM to none by mistake |
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2021-02-20 |
Luke Kenneth... | whoops spelling error |
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2021-02-20 |
Luke Kenneth... | add (unused) code for writing out SVSTATE in TestIssuer |
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2021-02-20 |
Luke Kenneth... | correct arguments, set microwatt_mmu=True, pass in... |
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2021-02-20 |
Luke Kenneth... | minor whitespace cleanup |
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2021-02-20 |
Luke Kenneth... | remove massive code-duplication, move simple "self... |
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2021-02-20 |
Tobias Platen | mmu testcase: set MMU SPRs |
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2021-02-20 |
Tobias Platen | add rom debugger |
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2021-02-20 |
Tobias Platen | add mmu rom testcase |
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2021-02-18 |
Tobias Platen | mmu: remove TestMemory |
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2021-02-17 |
Luke Kenneth... | declare blank classes SPEC and EXTRA2 to add MSB-to... |
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2021-02-17 |
Cesar Strauss | Use subfield bit selection to extract the RM SVP64... |
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2021-02-17 |
Cesar Strauss | Replace MSB-i by symbolic subfield indices and selectors |
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2021-02-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-17 |
Tobias Platen | add wishbone signals to gtkwave output |
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2021-02-17 |
Cesar Strauss | Add the SVSTATE traces to GTKWave to allow debugging... |
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2021-02-17 |
Cesar Strauss | Initialize the core SVSTATE from the corresponding... |
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2021-02-17 |
Cesar Strauss | Revert "Setup SVSTATE, from the test settings, at the... |
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2021-02-17 |
Cesar Strauss | Add a function to select bits from a signal into a... |
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2021-02-17 |
Luke Kenneth... | fix reg read/write in ISACaller, PowerDecoder2 handles... |
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2021-02-17 |
Cesar Strauss | Add a case for checking the EXTRA field and register... |
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2021-02-17 |
Cesar Strauss | Add traces to debug SVP64 prefix decoding issues |
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2021-02-17 |
Cesar Strauss | Setup SVSTATE, from the test settings, at the start |
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2021-02-16 |
Cesar Strauss | Fix MSB0 issues for SVP64 |
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2021-02-16 |
Tobias Platen | mmureq handling |
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2021-02-16 |
Tobias Platen | dcache error handling |
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2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-16 |
Luke Kenneth... | ordering wrong on svstate in ISACaller |
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2021-02-16 |
Luke Kenneth... | adapt botchify so it can be used for 31- or 15- etc... |
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2021-02-16 |
Luke Kenneth... | add indicator to PowerDecoder2 when no outputs are... |
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2021-02-15 |
Cole Poirier | remove file experiment/formal/proof_icache.py as it... |
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2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
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2021-02-15 |
Cesar Strauss | Simplify obtaining the PC from the register file |
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2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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next |