2020-09-12 |
Luke Kenneth... | whoops, indentation error |
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2020-09-12 |
Luke Kenneth... | enable Display debugs |
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2020-09-12 |
Luke Kenneth... | set bytesel in dcache store |
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2020-09-11 |
Luke Kenneth... | separat stbs_done into ld/st |
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2020-09-11 |
Luke Kenneth... | dcache load/store test |
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2020-09-11 |
Luke Kenneth... | debugging dcache |
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2020-09-11 |
Luke Kenneth... | wrong width for data / addr |
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2020-09-11 |
Luke Kenneth... | connect up WB SRAM to dcache test |
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2020-09-11 |
Luke Kenneth... | start on dcache test |
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2020-09-11 |
Luke Kenneth... | missing comb += |
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2020-09-11 |
Luke Kenneth... | missing maybe_tlb_plrus |
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2020-09-11 |
Luke Kenneth... | WAY_BITS not TLB_WAY_BITS |
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2020-09-11 |
Luke Kenneth... | whoops new node not to be calculated at end |
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2020-09-11 |
Luke Kenneth... | try to get better DTLBUpdate |
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2020-09-11 |
Luke Kenneth... | simplify dcache pending |
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2020-09-11 |
Luke Kenneth... | move dcache pending test to separate module |
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2020-09-11 |
Luke Kenneth... | more error correction in dcache |
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2020-09-11 |
Luke Kenneth... | use module for TLBUpdate |
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2020-09-11 |
Luke Kenneth... | add brackets round if & in dcache |
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2020-09-11 |
Cole Poirier | icache.py add test_icache and icache_sim derived from... |
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2020-09-11 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-09-11 |
Cole Poirier | icache.py fix spelling, syntax |
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2020-09-10 |
Luke Kenneth... | simplify read/write pte |
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2020-09-10 |
Luke Kenneth... | eek, big sort-out of syntax errors in dcache.py, now... |
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2020-09-10 |
Cole Poirier | icache.py rearrange the code within the base class... |
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2020-09-10 |
Luke Kenneth... | starting on dcache syntax errors |
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2020-09-10 |
Luke Kenneth... | add PLRU microwatt conversion |
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2020-09-10 |
Luke Kenneth... | add function calls to construct dcache |
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2020-09-10 |
Luke Kenneth... | correct some errors introduced in dcache.py |
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2020-09-10 |
Luke Kenneth... | add docstring for PowerOp class |
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2020-09-09 |
Luke Kenneth... | more laborious line-by-line checking of dcache.py conve... |
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2020-09-09 |
Cole Poirier | icache.py complete first translation pass of icache... |
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2020-09-08 |
Luke Kenneth... | add PowerDecoder explanation |
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2020-09-08 |
Luke Kenneth... | bit of a mess, trying to get PowerDecode to not create... |
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2020-09-08 |
Luke Kenneth... | subset columns for PowerDecoder - bit of a mess (done... |
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2020-09-08 |
Luke Kenneth... | create a special subset of Decoder Record for storing... |
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2020-09-08 |
Luke Kenneth... | pass in state into PowerDecode2, save on eqs and wires |
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2020-09-08 |
Luke Kenneth... | give Decode2Execute1Type in core a name |
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2020-09-08 |
Luke Kenneth... | argh, somehow EINT check got moved out of if/elif block |
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2020-09-08 |
Luke Kenneth... | capture trap / irq conditions in flags for debug purposes |
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2020-09-08 |
Luke Kenneth... | pass in CoreState to PowerDecoder rather than eq a... |
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2020-09-08 |
Luke Kenneth... | whoops trap address being set in wrong Decode2ExecuteTy... |
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2020-09-08 |
Luke Kenneth... | add cxxsim option |
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2020-09-07 |
Luke Kenneth... | use PowerDecoderSubsets for FUs, except for TRAP which... |
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2020-09-07 |
Luke Kenneth... | add per-FU PowerDecoders. should now be subsettable |
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2020-09-07 |
Luke Kenneth... | create eq_from function based on eq_from_execute1 |
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2020-09-07 |
Luke Kenneth... | debug print statement in eq_from_execute |
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2020-09-07 |
Luke Kenneth... | oe_ok renamed to oe, needed in regspec_decode_read |
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2020-09-07 |
Luke Kenneth... | add insn and fn_unit to CompLDSTOpSubset |
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2020-09-07 |
Luke Kenneth... | add pspec and opsubsetkls to CompUnits |
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2020-09-07 |
Cole Poirier | icache.py commit translation progress, about one third... |
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2020-09-07 |
Luke Kenneth... | make immediate decoding optional on-demand |
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2020-09-07 |
Luke Kenneth... | whoops spelling mistake outOut_carry not outPut_carry |
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2020-09-07 |
Luke Kenneth... | convert mul test to use Power Decode subset |
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2020-09-07 |
Luke Kenneth... | convert shift_rot to subset decoder |
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2020-09-07 |
Luke Kenneth... | convert branch test to PowerDecodeSubset form |
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2020-09-07 |
Luke Kenneth... | convert CR to PowerDecodeSubset format |
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2020-09-07 |
Luke Kenneth... | bit of a big reorg of data structures |
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2020-09-07 |
Luke Kenneth... | split out PowerDecode2 into PowerDecodeSubset |
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2020-09-07 |
Luke Kenneth... | large stack of moving stuff around in dcache |
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2020-09-07 |
Luke Kenneth... | adjust indentation of dcache_slow |
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2020-09-07 |
Luke Kenneth... | more dcache translation |
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2020-09-07 |
Luke Kenneth... | add start on cache_ram.vhdl to nmigen conversion |
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2020-09-07 |
Luke Kenneth... | more dcache translation |
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2020-09-07 |
Luke Kenneth... | allow Decode2ToExecute1Type to take an opkls argument |
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2020-09-07 |
Luke Kenneth... | whoops truncated the mb and me fields |
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2020-09-07 |
Luke Kenneth... | minor reorg on PowerDecoder |
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2020-09-06 |
Luke Kenneth... | comment, nothing unusual when Trap Type is DEC |
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2020-09-06 |
Luke Kenneth... | decoder immediate b split out to DecodeBImm |
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2020-09-06 |
Luke Kenneth... | decoder immediate a split out to DecodeAImm |
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2020-09-06 |
Luke Kenneth... | add row subset selector for PowerDecode. |
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2020-09-06 |
Luke Kenneth... | add row_subset (doesnt do anything yet) |
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2020-09-06 |
Luke Kenneth... | pass col_subset throughout PowerDecoder |
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2020-09-06 |
Luke Kenneth... | reorganise PowerOp to be dynamic |
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2020-09-06 |
Luke Kenneth... | reorg of PowerOp to be able to dynamically subset it |
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2020-09-06 |
Luke Kenneth... | grr, autopep8 messing up |
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2020-09-06 |
Luke Kenneth... | copy dec SPR into decoder cur_state |
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2020-09-06 |
Luke Kenneth... | add reset option to Register |
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2020-09-06 |
Luke Kenneth... | wark-wark, fast regs is binary-addressed |
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2020-09-06 |
Luke Kenneth... | add unit test for slow SPRs (SPRG0/1) |
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2020-09-06 |
Luke Kenneth... | minor code-munge on SPR-to-FAST mapping |
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2020-09-06 |
Luke Kenneth... | use with subTest in spr unit test |
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2020-09-06 |
Luke Kenneth... | redo generation of microwatt.v from litex |
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2020-09-06 |
Luke Kenneth... | add comments for DEC / TB |
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2020-09-06 |
Luke Kenneth... | add a DEC/TB FSM to TestIssuer |
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2020-09-06 |
Luke Kenneth... | move DEC and TB from StateRegs to FastRegs for several... |
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2020-09-06 |
Luke Kenneth... | add DEC SPR to CoreState and PowerDecoder, activate... |
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2020-09-06 |
Luke Kenneth... | add DEC and TB to State regfile |
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2020-09-06 |
Luke Kenneth... | add DEC/TB SPRs to spr pipeline |
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2020-09-05 |
Luke Kenneth... | add comments on MSR read |
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2020-09-05 |
Luke Kenneth... | move GPIO IRQ to 15 to match microwatt modifications |
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2020-09-05 |
Luke Kenneth... | hmmm XICS data being asserted on wb bus for too long |
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2020-09-05 |
Luke Kenneth... | argh missed a VHDL "&" translating to Cat |
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2020-09-05 |
Luke Kenneth... | reduce XICS address lookup by 2 bits |
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2020-09-05 |
Luke Kenneth... | MSR read in INSN_READ only occurs for 1 cycle |
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2020-09-05 |
Luke Kenneth... | sync on ICP eint |
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2020-09-05 |
Luke Kenneth... | connect XICS core irq to Decode2 eint |
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2020-09-05 |
Luke Kenneth... | whoops, combinatorial loop on pending_priority |
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2020-09-05 |
Luke Kenneth... | use stbcix in test |
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2020-09-05 |
Luke Kenneth... | XICS addresses in words: divide by 4 |
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next |