soc.git
2020-09-12 Luke Kenneth... whoops, indentation error
2020-09-12 Luke Kenneth... enable Display debugs
2020-09-12 Luke Kenneth... set bytesel in dcache store
2020-09-11 Luke Kenneth... separat stbs_done into ld/st
2020-09-11 Luke Kenneth... dcache load/store test
2020-09-11 Luke Kenneth... debugging dcache
2020-09-11 Luke Kenneth... wrong width for data / addr
2020-09-11 Luke Kenneth... connect up WB SRAM to dcache test
2020-09-11 Luke Kenneth... start on dcache test
2020-09-11 Luke Kenneth... missing comb +=
2020-09-11 Luke Kenneth... missing maybe_tlb_plrus
2020-09-11 Luke Kenneth... WAY_BITS not TLB_WAY_BITS
2020-09-11 Luke Kenneth... whoops new node not to be calculated at end
2020-09-11 Luke Kenneth... try to get better DTLBUpdate
2020-09-11 Luke Kenneth... simplify dcache pending
2020-09-11 Luke Kenneth... move dcache pending test to separate module
2020-09-11 Luke Kenneth... more error correction in dcache
2020-09-11 Luke Kenneth... use module for TLBUpdate
2020-09-11 Luke Kenneth... add brackets round if & in dcache
2020-09-11 Cole Poiriericache.py add test_icache and icache_sim derived from...
2020-09-11 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-09-11 Cole Poiriericache.py fix spelling, syntax
2020-09-10 Luke Kenneth... simplify read/write pte
2020-09-10 Luke Kenneth... eek, big sort-out of syntax errors in dcache.py, now...
2020-09-10 Cole Poiriericache.py rearrange the code within the base class...
2020-09-10 Luke Kenneth... starting on dcache syntax errors
2020-09-10 Luke Kenneth... add PLRU microwatt conversion
2020-09-10 Luke Kenneth... add function calls to construct dcache
2020-09-10 Luke Kenneth... correct some errors introduced in dcache.py
2020-09-10 Luke Kenneth... add docstring for PowerOp class
2020-09-09 Luke Kenneth... more laborious line-by-line checking of dcache.py conve...
2020-09-09 Cole Poiriericache.py complete first translation pass of icache...
2020-09-08 Luke Kenneth... add PowerDecoder explanation
2020-09-08 Luke Kenneth... bit of a mess, trying to get PowerDecode to not create...
2020-09-08 Luke Kenneth... subset columns for PowerDecoder - bit of a mess (done...
2020-09-08 Luke Kenneth... create a special subset of Decoder Record for storing...
2020-09-08 Luke Kenneth... pass in state into PowerDecode2, save on eqs and wires
2020-09-08 Luke Kenneth... give Decode2Execute1Type in core a name
2020-09-08 Luke Kenneth... argh, somehow EINT check got moved out of if/elif block
2020-09-08 Luke Kenneth... capture trap / irq conditions in flags for debug purposes
2020-09-08 Luke Kenneth... pass in CoreState to PowerDecoder rather than eq a...
2020-09-08 Luke Kenneth... whoops trap address being set in wrong Decode2ExecuteTy...
2020-09-08 Luke Kenneth... add cxxsim option
2020-09-07 Luke Kenneth... use PowerDecoderSubsets for FUs, except for TRAP which...
2020-09-07 Luke Kenneth... add per-FU PowerDecoders. should now be subsettable
2020-09-07 Luke Kenneth... create eq_from function based on eq_from_execute1
2020-09-07 Luke Kenneth... debug print statement in eq_from_execute
2020-09-07 Luke Kenneth... oe_ok renamed to oe, needed in regspec_decode_read
2020-09-07 Luke Kenneth... add insn and fn_unit to CompLDSTOpSubset
2020-09-07 Luke Kenneth... add pspec and opsubsetkls to CompUnits
2020-09-07 Cole Poiriericache.py commit translation progress, about one third...
2020-09-07 Luke Kenneth... make immediate decoding optional on-demand
2020-09-07 Luke Kenneth... whoops spelling mistake outOut_carry not outPut_carry
2020-09-07 Luke Kenneth... convert mul test to use Power Decode subset
2020-09-07 Luke Kenneth... convert shift_rot to subset decoder
2020-09-07 Luke Kenneth... convert branch test to PowerDecodeSubset form
2020-09-07 Luke Kenneth... convert CR to PowerDecodeSubset format
2020-09-07 Luke Kenneth... bit of a big reorg of data structures
2020-09-07 Luke Kenneth... split out PowerDecode2 into PowerDecodeSubset
2020-09-07 Luke Kenneth... large stack of moving stuff around in dcache
2020-09-07 Luke Kenneth... adjust indentation of dcache_slow
2020-09-07 Luke Kenneth... more dcache translation
2020-09-07 Luke Kenneth... add start on cache_ram.vhdl to nmigen conversion
2020-09-07 Luke Kenneth... more dcache translation
2020-09-07 Luke Kenneth... allow Decode2ToExecute1Type to take an opkls argument
2020-09-07 Luke Kenneth... whoops truncated the mb and me fields
2020-09-07 Luke Kenneth... minor reorg on PowerDecoder
2020-09-06 Luke Kenneth... comment, nothing unusual when Trap Type is DEC
2020-09-06 Luke Kenneth... decoder immediate b split out to DecodeBImm
2020-09-06 Luke Kenneth... decoder immediate a split out to DecodeAImm
2020-09-06 Luke Kenneth... add row subset selector for PowerDecode.
2020-09-06 Luke Kenneth... add row_subset (doesnt do anything yet)
2020-09-06 Luke Kenneth... pass col_subset throughout PowerDecoder
2020-09-06 Luke Kenneth... reorganise PowerOp to be dynamic
2020-09-06 Luke Kenneth... reorg of PowerOp to be able to dynamically subset it
2020-09-06 Luke Kenneth... grr, autopep8 messing up
2020-09-06 Luke Kenneth... copy dec SPR into decoder cur_state
2020-09-06 Luke Kenneth... add reset option to Register
2020-09-06 Luke Kenneth... wark-wark, fast regs is binary-addressed
2020-09-06 Luke Kenneth... add unit test for slow SPRs (SPRG0/1)
2020-09-06 Luke Kenneth... minor code-munge on SPR-to-FAST mapping
2020-09-06 Luke Kenneth... use with subTest in spr unit test
2020-09-06 Luke Kenneth... redo generation of microwatt.v from litex
2020-09-06 Luke Kenneth... add comments for DEC / TB
2020-09-06 Luke Kenneth... add a DEC/TB FSM to TestIssuer
2020-09-06 Luke Kenneth... move DEC and TB from StateRegs to FastRegs for several...
2020-09-06 Luke Kenneth... add DEC SPR to CoreState and PowerDecoder, activate...
2020-09-06 Luke Kenneth... add DEC and TB to State regfile
2020-09-06 Luke Kenneth... add DEC/TB SPRs to spr pipeline
2020-09-05 Luke Kenneth... add comments on MSR read
2020-09-05 Luke Kenneth... move GPIO IRQ to 15 to match microwatt modifications
2020-09-05 Luke Kenneth... hmmm XICS data being asserted on wb bus for too long
2020-09-05 Luke Kenneth... argh missed a VHDL "&" translating to Cat
2020-09-05 Luke Kenneth... reduce XICS address lookup by 2 bits
2020-09-05 Luke Kenneth... MSR read in INSN_READ only occurs for 1 cycle
2020-09-05 Luke Kenneth... sync on ICP eint
2020-09-05 Luke Kenneth... connect XICS core irq to Decode2 eint
2020-09-05 Luke Kenneth... whoops, combinatorial loop on pending_priority
2020-09-05 Luke Kenneth... use stbcix in test
2020-09-05 Luke Kenneth... XICS addresses in words: divide by 4
next